International Business Machines Corporation

Other

Globalfoundries Inc.

David J Webb

Peter L Buchmann

Peter Vettiger

Andreas Guenther Herkersdorf

Fabrice Jean Verplanken

Jean Louis Calvignac

Michel Despont

Bert Jan Offrein

Otto Voegeli

Kenneth James Barker

Rolf Clauberg

Laurent A Dellmann

Devendra K Sadana

Steven John Koester

Edward William Kiewra

Jean Fompeyrine

Ronald Pete Luijten

Fritz R Gfeller

Christoph S Harder

Antonius Paulus Engbersen

Gian-Luca Bona

Peter D Hoh

Ronald Peter Luijten

Heinz Jaeckel

Hanspeter Ott

Wilhelm Heuberger

Hans Peter Dietrich

Fran&ccedil;ois G Abel

A method of forming a high k gate stack on a surface of a III-V compound semiconductor, such GaAs, is provided. The method includes subjecting a III-V compound semiconductor material to a precleaning process which removes native oxides from a surface of the III-V compound semiconductor material; forming a semiconductor, e.g., amorphous Si, layer in-situ on the cleaned surface of the III-V compound semiconductor material; and forming a dielectric material having a dielectric constant that is greater than silicon dioxide on the semiconducting layer. In some embodiments, the semiconducting layer is partially or completely converted into a layer including at least a surface layer that is comprised of AONprior to forming the dielectric material. In accordance with the present invention, A is a semiconducting material, preferably Si, x is 0 to 1, y is 0 to 1 and x and y are both not zero.

High &#x3ba; gate stack on III-V compound semiconductors

The present invention relates to a device for combining at least two data signals having an input data rate into a single data stream having an output data rate being higher than the input data rate for transmission on a shared medium or vice versa, particularly, to a single SDH/SONET framer capable of handling a large range of SDH/SONET frames from STM-i to STM-j with an aggregated total capacity corresponding to an STM-j frame where i and j are integers in the range from 1 to 64 or higher according to the STM-N definition of the SDH/SONET standards. More over, the present invention can also be extended to work with STS-1 as lowest range. STS-1 exists in SONET only not SDH and corresponds to a data rate of 51.5 Mb/s a third of the 156 Mb/s of STM-1. The device according to the present invention comprises at least two ports for receiving and/or sending said at least two data signals, a port scanning unit for extracting data from the data signals received by said ports and/or synthesizing data to be transmitted via the ports, respectively, whereby said port scanning unit is configured to extract data from ports providing data streams having at least two different input data rates and/or to synthesize data to be transmitted via the ports taking data streams having at least two different data rates.

STM-1 to STM-64 SDH/SONET framer with data multiplexing from a series of configurable I/O ports

An opto-electronic board including a printed wiring board with an optical waveguide, a metallic area, and a hole, wherein an abutting face of the optical waveguide and an abutting face of the metallic area form a part of the side face of the hole. The opto-electronic board further comprises an opto-electronic circuit with a bonding pad, wherein the opto-electronic circuit is arranged in the hole and soldered with its bonding pad to the abutting face of the metallic area.

Opto-electronic board

A real-time load-balancing system for distributing a sequence of incoming data packets emanating from a high speed communication line to a plurality of processing means, each operating at a capacity that is lower than the capacity of the high speed communication line; the system according to the invention comprises: a parser capable of extracting a configurable set of classifier bits from the incoming packets for feeding into a compression means; the compression means is capable of reducing a bit pattern of length K to a bit pattern having a length L which is a fraction of K; a pipeline block for delaying incoming packets until a load balancing decision is found, and an inverse demultiplexer for receiving a port identifier output from said compression means as selector and for directing pipelined packets to the appropriate output port.

Load balancing system, apparatus and method

Method and apparatus for ATM switching

Optoelectronic composite consisting of two chips, the first chip 10 being made of a first material, the second one 13 being made of another material. The first chip 10, for example, comprises a multiplicity of active optoelectronic devices e.g. a laser diode 11 and a photo diode 12, all being monolithically integrated. A multiplicity of other optical devices, e.g. a waveguide 16, is monolithically integrated on the second chip 13. In addition this second chip 13 has depressions of the size of the devices 11,12 integrated on said first chip 10. These devices and the waveguide 16 of the second chip 13 are automatically aligned when flipping both chips together.

Bilithic composite for optoelectronic integration

Automatic alignment of an optical waveguide to a ridge waveguide laser is accomplished by transferring the ridge structure of the laser to a substrate by etching a mirror groove. The transferred ridge structure serves as a base for the deposition of waveguide layers. The thickness of the waveguide layers are controlled during the deposition such that the waveguide core is laterally and vertically aligned to the lasing active layer of the laser structure.

Self-aligned optical waveguide to laser structure and method for making

A method of passivating etched mirror facets of semiconductor laser diodes which enhances device reliability. The etched mirror facet is first subjected to a weet-etch process to substantially remove any native oxide as well as any surface layer which may have been mechanically damaged during the preceding mirror etch process. Then, a passivation pre-treatment is applied whereby any residual oxygen is removed and a sub-monolayer is formed which permanently reduces the non-radiative recombination of minority carriers at the mirror facet. Finally, the pre-treated mirror surface is coated with a passivation layer to avoid any environmental effect on the mirror.

Method of passivating etched mirror facets of semiconductor laser diodes

A method, and device produced therewith, for improving the planarity of etched mirror facets 18 of integrated optic structures with non-planar stripe waveguides, such as ridge or groove diode lasers or passive devices such as modulators and switches. The curvature of the mirror facet surface at the edges of the waveguide due to topographical, lithographical and etch process effects, causes detrimental phase distortions, and is avoided by widening the waveguide end near the mirror surface thereby shifting the curved facet regions away from the light mode region to surface regions where curvature is not critical.

Improved planar etched mirror facets

A process for forming the ridge structure of a self-aligned InP-system, double heterostructure (DH) laser, particularly useful for long wavelength devices as required for signal transmission systems includes a thin Si.sub.3 N.sub.4 layer (41) inserted between a photoresist mask (42) that defines the ridge structure, and a contact layer (35). Using a Si.sub.3 N.sub.4 layer (4) deposited at a high plasma excitation frequency (RF) for adhesion promotion, and a low frequency deposited (LF) Si.sub.3 N.sub.4 layer (43) for device embedding, provides for the etch selectively required in the process step that is used to expose the contact layer to ohmic contact metallization deposition.

Process for forming the ridge structure of a self-aligned semiconductor

Method for improving the planarity of etched mirror facets

A method and apparatus for maintaining orientation of a wafer with respect to the wafer holder and a source emission is disclosed. Briefly stated, a wafer is disposed on a wafer holder and displaced in translation only while made to continuously follow a planar closed path which allows the rotation of the wafer with respect to source of emission while keeping the wafer and the wafer holder uniformly aligned with respect to each other.

Wafer holder method and apparatus in a vacuum deposition system

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Ruschlikon, Switzerland

David J Webb