Kla Tencor Corporation

Kla-tencor Technologies Corporation

David J Walker

David Lewis Adler

Akella V S Satya

Gustavo A Pinto

Neil W Richardson

Robert Thomas Long

Brian C Leslie

Fred Babian

Travis Wolfe

Kurt H Weiner

Bin-Ming Benjamin Tsai

Lynda C Mantalas

Mark Armstrong McCord

Marian Mankos

Salam Harb

David G Stites

Jun Pei

Vassil Spasov

Padma A Satya, Legal Representative

Izzy Lewis

Disclosed is a method of inspecting a sample. The sample is scanned in a first direction with at least one particle beam. The sample is scanned in a second direction with at least one particle beam. The second direction is at an angle to the first direction. The number of defects per an area of the sample are found as a result of the first scan, and the position of one or more of the found defects is determined from the second scan. In a specific embodiment, the sample includes a test structure having a plurality of test elements thereon. A first portion of the test elements is exposed to the beam during the first scan to identify test elements having defects, and a second portion of the test elements is exposed during the second scan to isolate and characterize the defect.

Multiple directional scans of test structures on semiconductor integrated circuits

One embodiment relates to an apparatus for inspecting a substrate using charged particles. The apparatus includes an illumination subsystem, an objective subsystem, a projection subsystem, and a beam separator interconnecting those subsystems. The apparatus further includes a detection system which includes a scintillating screen, a detector array, and an optical coupling apparatus positioned therebetween. The optical coupling apparatus includes both refractive and reflective elements. Other embodiments and features are also disclosed.

High-resolution, low-distortion and high-efficiency optical coupling in detection system of electron beam apparatus

An apparatus and method for inspecting a surface of a sample, particularly but not limited to a semiconductor device, using an electron beam is presented. The technique is called Secondary Electron Emission Microscopy (SEEM), and has significant advantages over both Scanning Electron Microscopy (SEM) and Low Energy Electron Microscopy (LEEM) techniques. In particular, the SEEM technique utilizes a beam of relatively high-energy primary electrons having a beam width appropriate for parallel, multi-pixel imaging. The electron energy is near a charge-stable condition to achieve faster imaging than was previously attainable with SEM, and charge neutrality unattainable with LEEM. The emitted electrons may be detected using a time delay integration detector.

Apparatus and method for secondary electron emission microscope

Disclosed is a semiconductor die having a scanning area. The semiconductor die includes a first plurality of test structures wherein each of the test structures in the first plurality of test structures is located entirely within the scanning area. The semiconductor die further includes a second plurality of test structures wherein each of the test structures in the first plurality of test structures is located only partially within the scanning area. The test structures are arranged so that a scan of the scanning area results in detection of defects outside of the scanning area.

Test structures and methods for inspection of semiconductor integrated circuits

Disclosed is a method for detecting electrical defects on test structures of a semiconductor die. The test structures includes a plurality of electrically-isolated test structures and a plurality of non-electrically-isolated test structures. The test structures each has a portion located partially within a scan area. The portion of the test structures located within the scan area is scanned to obtain voltage contrast images of the test structures' portions. In a multi-pixel processor, the obtained voltage contrast images are analyzed to determine whether there are defects present within the test structures. In a preferred embodiment, the multi-pixel processor operates with pixel resolution sizes in a range of about 25 nm to 200 nm. In another aspect, the processor operates with a pixel size nominally equivalent to two times a width of the test structure's line width to maximize throughput at optimal signal to noise sensitivity. A computer readable medium having programming instructions for performing the above described methods is also disclosed.

Multi-pixel methods and apparatus for analysis of defect information from test structures on semiconductor devices

Disclosed is a semiconductor die having an upper layer and a lower layer. The die includes a lower test structure formed in the lower metal layer of the semiconductor die. The lower conductive test structure has a first end and a second end, wherein the first end is coupled to a predetermined voltage level. The die also has an insulating layer formed over the lower metal layer and an upper test structure formed in the upper metal layer of the semiconductor die. The upper conductive test structure is coupled with the second end of the lower conductive test structure, and the upper metal layer being formed over the insulating layer. The die further includes at least one probe pad coupled with the upper test structure. Preferably, the first end of the lower test structure is coupled to a nominal ground potential. In another implementation, the upper test structure is a voltage contrast element. In another embodiment, a semiconductor die having a scanning area is disclosed. The semiconductor die includes a first plurality of test structures wherein each of the test structures in the first plurality of test structures is located entirely within the scanning area. The die includes a second plurality of test structures wherein each of the test structures in the first plurality of test structures is located only partially within the scanning area. The first plurality of test structures or the second plurality of test structures has a probe pad coupled to at least one test structure.

Dual probe test structures for semiconductor integrated circuits

Disclosed is a method of inspecting a sample. The method includes moving to a first field associated with a first group of test structures. The first group of test structures are partially within the first field. The method further includes scanning the first field to determine whether there are any defects present within the first group of test structures. When it is determined that there are defects within the first group of test structures, the method further includes repeatedly stepping to areas and scanning such areas so as to determine a specific defect location within the first group of test structures. A suitable test structure for performing this method is also disclosed.

Stepper type test structures and methods for inspection of semiconductor integrated circuits

Simultaneous flooding and inspection for charge control in an electron beam inspection machine

A sample is inspected. The sample is scanned in a first direction with at least one particle beam. The sample is scanned in a second direction with at least one particle beam. The second direction is at an angle to the first direction. The number of defects per an area of the sample are found as a result of the first scan, and the position of one or more of the found defects is determined from the second scan. In a specific embodiment, the sample includes a test structure having a plurality of test elements thereon. A first portion of the test elements is exposed to the beam during the first scan to identify test elements having defects, and a second portion of the test elements is exposed during the second scan to isolate and characterize the defect.

Disclosed is, a method for detecting electrical defects on test structures of a semiconductor die. The semiconductor die includes a plurality of electrically-isolated test structures and a plurality of non-electrically-isolated test structures. Voltages are established for the plurality of electrically-isolated test structures. These voltages are different than the voltages of the plurality of non-electrically-isolated test structures. A region of the semiconductor die is continuously inspected in a first direction thereby obtaining voltage contrast data indicative of whether there are defective test structures. The voltage contrast data is analyzed to determine whether there are one or more defective test structures.

Growing community of inventors

Sunol, CA, United States of America

David J Walker