International Business Machines Corporation

David J Wager

Michael Richard Ouellette

Wayne Frederick Ellis

Robert C Wong

Randy William Mann

Jeremy Paul Rowland

Igor Arsovski

Michael Anthony Ziegerhofer

Michael Thomas Fragano

Ciaran J Brennan

Steven Michael Eustis

Neelesh Govindaraya Pai

Kevin M Tompsett

Disclosed is a semiconductor chip with a digital integrated circuit, such as a memory device (e.g., static random access memory (SRAM) arrays, dynamic random access memory (DRAM) arrays, content addressable memory (CAM) arrays, etc), that can be selectively operated in either a functional mode or in a performance screening mode. In the functional mode, a first signal supplied by an external signal generator is used to activate a first device in the circuit and, in response, a second device in the circuit outputs a data output signal. In the performance screening mode, a second signal is internally generated by an internal signal generator based on the data output signal. This second signal is then used to activate the first device in the circuit and, in response, the second device outputs the data output signal. Thus, in the performance screening mode, the digital integrated circuit is effectively converted into a performance screen ring oscillator (PSRO), the output of which can be monitored to determine whether performance criteria for the digital integrated circuit are met.

Circuit structure and method for digital integrated circuit performance screening

A design process includes inputting a design file representing a circuit design embodied in a non-transitory computer-readable medium, and using a computer to translate the circuit design into a netlist. The netlist comprises a representation of a plurality of wires, transistors, and logic gates, and is stored in the non-transitory computer-readable medium. When executed by the computer, the netlist produces the circuit design. The circuit design comprises a static random access memory ('SRAM') including a plurality of SRAM cells arranged in an array, including a plurality of rows and a plurality of columns, and a plurality of column voltage control circuits corresponding to respective ones of the plurality of columns of the array. Each of the plurality of voltage control circuits is coupled to an output of a power supply and is operable to temporarily reduce a voltage upon arrival of a bit select signal provided to power supply inputs of a plurality of SRAM cells belonging to a selected column of the plurality of columns. The selected column is selected during a write operation in which a bit is written to one of the plurality of SRAM cells belonging to the selected column. Each column voltage control circuit includes an NFET and a pair of PFETs. Each NFET and pair of PFETs has a conduction path directly connected between the output of the power supply and the power supply inputs of the plurality of SRAM cells.

Circuit design

A static random access memory ('SRAM') is provided which includes a plurality of SRAM cells arranged in an array having a plurality of portions. The SRAM includes a plurality of voltage control circuits corresponding to respective ones of the plurality of portions of the array. Each of the plurality of voltage control circuits is coupled to an output of a power supply, each voltage control circuit having a function to temporarily reduce a voltage provided to power supply inputs of a plurality of SRAM cells that belong to a selected one of the plurality of portions of the SRAM. The power supply voltage to the selected portion is reduced during a write operation in which a bit is written to one of the SRAM cells belonging to the selected portion.

SRAM voltage control for improved operational margins

A static random access memory ('SRAM') is provided which includes a plurality of SRAM cells arranged in an array. The array includes a plurality of rows and a plurality of columns. The SRAM includes a plurality of voltage control corresponding to respective ones of the plurality of columns of the array. Each of the plurality of voltage control circuits are coupled to an output of a power supply, each voltage control circuit having a function to temporarily reduce a voltage provided to power supply inputs of a plurality of SRAM cells that belong to a selected column of columns of the SRAM. The selected column is selected and the power supply voltage to that column is reduced during a write operation in which a bit is written to one of the SRAM cells belonging to the selected column.

A method of manufacturing a device having embedded memory including a plurality of memory cells. During manufacturing test, a first test stress is applied to selected cells of the plurality of memory cells with a built-in self test. At least one weak memory cell is identified. The at least one weak memory cell is repaired. A second test stress is applied to the selected cells and the repaired cells with the built-in self test.

Method and apparatus for test and repair of marginally functional SRAM cells

A method and apparatus for testing a write function of a dual-port static memory cell during a concurrent read/write cycle on a memory cell is disclosed. A memory cell of a dual-port static memory is read via a first port of the memory cell. After the read operation, the standard bitline restore operation that normally occurs after a read or write operation is suppressed from occurring on the bitlines for the first port. Then, the memory cell is read again via the first port at the same time the memory cell is being written via a second port with a logical data value that is opposite to the logical data value being read from the first port. After the completion of the write operation, the bitlines for the first and second ports are restored by a bitline restore operation. Finally, the logical data value in the memory cell is verified for its correctness.

Method and apparatus for testing a write function of a dual-port static memory cell

A structure and method for testing multi-port SRAM cells includes a test controller connected to at least one multi-port SRAM cell (the test controller is adapted to store a pattern into the multi-port SRAM cell and generate a stability test restore clamp), a read/write controller connected to the multi-port SRAM cell (the read/write controller is adapted to simultaneously activate a plurality of wordline ports on the multi-port SRAM cell while the stability test restore clamp is enabled), and a timing control circuit connected to the read/write controller. The timing control circuit is adapted to vary an activation time of the wordline ports. The read/write controller reads from the multi-port SRAM after the stability test restore clamp is deactivated. The read/write controller activates the wordline ports for each multi-port SRAM cell in an array sequentially while all bitlines in the array are held on by the stability test restore clamp. The structure also includes a logic device connected to the test controller adapted to prevent the stability test restore clamp from being enabled unless a test is being performed. The timing control circuit is adapted to be selectively externally controllable to vary the activation time of the wordline ports. The timing control circuit can include a plurality of delay units adapted to be selectively engaged to vary the activation time of the wordline ports. The stability test restore clamp is enabled for at least a wordline pulse.

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Jericho, VT, United States of America

David J Wager