Intel Corporation

Northwestern University

David J Towner

Dragos Seghete

Christopher R Ryder

Tahir Ghani

Uygar E Avci

Oleg Golonzka

Mohit K Haran

Bruce W Wessels

Dax M Crum

Christopher M Pelto

Dan S Lavric

Orb Acton

Jitendra Kumar Jha

Che-Yun Lin

Aaron J Welsh

Anthony V Mule'

Angel Aquino Gonzalez

Takayoshi Ito

Stephanie F Sundholm

Mark A Blount

Pingsheng Tang

Anil W Dey

Anthony L Meier

Chamara Abeysekera

YenTing Chiu

An integrated circuit structure comprises a first and second vertical arrangement of horizontal nanowires in a PMOS region and in an NMOS region. A first gate stack having a P-type conductive layer surrounds the first vertical arrangement of horizontal nanowires. A second gate stack surrounds the second vertical arrangement of horizontal nanowires. In one embodiment, the second gate stack has an N-type conductive layer, the P-type conductive layer is over the second gate stack, and an N-type conductive fill is between N-type conductive layer and the P-type conductive layer to provide same polarity metal filled gates. In another embodiment, the second gate stack has an N-type conductive layer comprising Titanium (Ti) and 'Nitrogen (N) having a low saturation thickness of 3-3.5 nm surrounding the nanowires, and the N-type conductive layer is covered by the P-type conductive layer.

Gate-all-around integrated circuit structures having uniform threshold voltages and tight gate endcap tolerances

Multi-layer etch stop layers are described. In an example, an integrated circuit structure includes a conductive line in a first interlayer dielectric material above a substrate. A first dielectric etch stop layer, a second dielectric layer and a third dielectric layer are on the conductive line and the first interlayer dielectric material. A second interlayer dielectric material is on the third dielectric etch stop layer. An opening is in the second interlayer dielectric material, in the third dielectric etch stop layer, and in the second dielectric etch stop layer, in the first dielectric etch stop layer. A conductive structure is in the opening, the conductive structure in direct contact with the conductive line.

Multi-layer etch stop layers for advanced integrated circuit structure fabrication

Metal insulator metal capacitors are described. In an example, a capacitor includes a first electrode plate, and a first capacitor dielectric on the first electrode plate. A second electrode plate is on the first capacitor dielectric and is over and parallel with the first electrode plate, and a second capacitor dielectric is on the second electrode plate. A third electrode plate is on the second capacitor dielectric and is over and parallel with the second electrode plate, and a third capacitor dielectric is on the third electrode plate. A fourth electrode plate is on the third capacitor dielectric and is over and parallel with the third electrode plate. In another example, a capacitor includes a first electrode, a capacitor dielectric on the first electrode, and a second electrode on the capacitor dielectric. The capacitor dielectric includes a plurality of alternating first dielectric layers and second dielectric layers.

Metal insulator metal (MIM) capacitor

Electro-optic modulator devices and related waveguide components comprising BaTiOfilms.

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Growing community of inventors

Portland, OR, United States of America

David J Towner