Texas Instruments Corporation

David J Toops

Yunchen Qiu

Sudhir Kumar Madan

Harold L Davis

Xiaowei Deng

Bryan David Sheffield

Michael Patrick Clinton

Robert L Pitts

Robert J Landers

George B Jamison

Suresh Balasubramanian

Tam Minh Tran

Vikas K Agrawal

An example memory circuit for reading and/or writing FRAM memory includes a controller to output a signal to an input of a driver; a transistor coupled an output of the driver; the driver to, in response to receiving the signal, output a first voltage to the transistor; and the transistor to, in response to receiving the first voltage, output a second voltage to a bit cell after a transistor delay, the transistor selected based on a size of the memory circuit.

Time tracking circuit for FRAM

A semiconductor device includes a ROM, a differential sense amplifier and a multiplexer logic circuit. The ROM has memory cells in rows along word lines and columns along bit lines, and a reference column having reference transistors along a reference bit line. The multiplexer logic circuit couples a selected bit line to a first differential amplifier input and couples the reference bit line to the second differential amplifier input and controls a reference current of the reference bit line to be between a first bit line current of a programmed memory cell and a second bit line current of an unprogrammed memory cell.

High speed differential rom

A delay circuit includes precharge and discharge transistors configured to receive an input signal. The delay circuit also includes a resistor coupled to the precharge transistor having a negative temperature coefficient to thereby form a node. A capacitive device and an inverter are coupled to the node. The inverter produces an output signal. Responsive to the input signal having a first polarity, the precharge transistor is configured to be turned on and the discharge transistor is configured to be turned off to thereby cause current to flow through the precharge transistor to the capacitive device to thereby charge the capacitive device. Responsive to the input signal having a second polarity, the precharge and discharge transistors are configured to change state to thereby cause charge from the capacitive device to discharge through the resistor and through the discharge transistor. The voltage on the node decays to a level which eventually causes the inverter's output to change state.

Resistor-capacitor (RC) delay circuit with a precharge mode

In one example a semiconductor device has a data latch that includes first and second transmission gates and first and second inverters. The first inverter is connected between a first terminal of the first transmission gate and a first terminal of the second transmission gate. The second inverter is connected between a second terminal of the first transmission gate and a second terminal of the second transmission gate. The data latch is configured to store a datum received at the connection between the first transmission gate and the second inverter, and to store a datum received at the connection between the second transmission gate and the first inverter.

Sense amplifier look-through latch for FAMOS-based EPROM

Methods and apparatus for reading and/or writing FRAM memory are disclosed. An example memory circuit includes a controller to output a signal to an input of a driver; a transistor coupled an output of the driver; the driver to, in response to receiving the signal, output a first voltage to the transistor; and the transistor to, in response to receiving the first voltage, output a second voltage to a bit cell after a transistor delay, the transistor selected based on a size of the memory circuit.

A programmable memory including a self-latching read data path. A sense amplifier senses the voltage level at a bit line, the bit line communicating the data state of a selected memory cell in its associated column. A data latch coupled to the output of the sense amplifier passes the sensed data state. Set-reset logic is provided that receives the output of the data latch in the read data path and, in response to a transition of the data state in a read cycle, latches the data latch and isolates it from the sense amplifier. The set-reset logic resets the data latch at the start of the next read cycle. In some embodiments, a timer is provided so that the latch is reset after a time-out period in a long read cycle in which no data transition occurs.

Self-latch sense timing in a one-time-programmable memory architecture

A computer program for generating a layout for a ferroelectric random access memory (FRAM) that is embodied on a non-transitory storage medium and executable by a processor is provided. FRAM specifications are received, and an FRAM floorplan and design rules are retrieved from the non-transitory storage medium. The layout for the FRAM based on the FRAM specifications and design rules is then assembled.

FRAM compiler and layout

An integrated circuit containing a memory array, a redundancy circuit and a redundancy error correction circuit coupled to said redundancy circuit. A method for constructing a redundancy word which corresponds to each memory segment and a method for error checking the redundancy word during a memory access request.

High reliability and low power redundancy for memory

A static RAM redundancy memory for use in combination with a non-volatile memory array, such as ferroelectric RAM (FRAM), in which the power consumption of the SRAM redundancy memory is reduced. Each word of the redundancy memory includes data bit cells for storing addresses of memory cells in the FRAM array to be replaced by redundant elements, and also enable bits indicating whether redundancy is enabled for those addresses. A logical combination of the enable bits in a given word determines whether the data bit cells in that word are powered-up. As a result, the power consumption of the redundancy memory is reduced to the extent that redundancy is not enabled for segments of the FRAM array.

Low-power redundancy for non-volatile memory

According to one embodiment of the present invention a memory subsystem comprises a column and a column select signal line. The column comprises at least one bit line and a write precharge circuit. The write precharge circuit is operable to provide at least a portion of a charge on the at least one bit line. The column select signal line is operable to provide a column select signal selecting the column for a write operation. The write precharge circuit is gated with the column select signal line such that the column select signal is communicated to the write precharge circuit upon selection of the column for the write operation. The write precharge circuit is operable to at least partially restore the charge on the at least one bit line upon receipt of the column select signal after the write operation.

Method and apparatus for optimal write restore for memory

In accordance with one embodiment of the present invention, a memory array includes a plurality of memory cells, the memory cells each comprising one or more gates, and a word line for controlling the gates of the plurality of memory cells. A driver is coupled to the word line at a first location. The driver is operable to drive the gates of the memory cells. A load device is coupled to the word line at a second location remote from the first location. The load device is operable to pull a set of gates electrically isolated from the driver to a substantially non-floating state.

System and method for pulling electrically isolated memory cells in a memory array to a non-floating state

According to one embodiment of the invention, a memory circuit operable to assume a standby mode is provided. A memory circuit includes a transistor comprising a gate and a bulk. The bulk is at a retention voltage level. The memory circuit also includes a first node and a second node that are coupled to each other by the transistor. The first node is operable to assume a higher voltage level than the second node in response to an initiation of the standby mode. The memory circuit also includes a third node coupled to the gate of the transistor. The third node is operable to assume a voltage approximately equal to the retention voltage in response to an initiation of the standby mode. The transistor is operable to reduce any direct current flow between the first node and the second node in response to a rise in voltage at the third node to a voltage approximately equal to the retention voltage.

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Lucas, TX, United States of America

David J Toops