Unisys Corporation

Sperry Corporation

David J Tanglin

Larry L Byers

Gregory B Wiedenman

John T Rusterholz

James R Hamstra

Lawrence R Fontaine

Michael Danilenko

Paul A Laberge

Howard A Koehler

A power loss detection and recovery circuit for providing continued memory operations upon loss of a supply voltage. Multiple independent power domains, each of which provides an electrically isolated supply voltage, are used to provide power to redundant memory circuitry. A loss of voltage or a degenerative voltage within a power domain is detected, and circuitry residing on a different operational power domain provides recovery operations to allow continued memory activity within that operational power domain. The memories residing in an adjacent pair of power domains redundant, and are therefore written to and read from simultaneously, and circuitry within an operational power domain will prevent further reading of data from the memory residing in a failed power domain, and will also prevent further writing of data to the memory residing in the failed power domain upon recognition of a failed supply voltage within a power domain.

Multiple power domain power loss detection and interface disable

A multi-function high speed sequencer is provided in a high speed instruction processor. The high speed sequencer comprises a first input latch coupled to logic signals for producing a first sequence signal. A chain of alternately clocked even and odd principal latches are coupled to the output of the first input latch to produce even and odd principal sequence signals for accessing a high speed MSU. A plurality of staging latches are coupled between the odd and the even principal latches for producing even and odd secondary sequence signals for accessing a slower speed MSU.

Multi-function timing sequencer for different speed main storage units

A local store for a scientific vector processor which provides high speed access to scalar variables, parameters, temporary operands, and register save area contents of the system. Basically, the local store is a general purpose storage structure which provides access which is as fast as access to the general or vector registers of the vector processor. It is capable of being accessed either directly or indirectly via indexing. It resides in the virtual address area of the machine so that it is accessible for either reading or writing by the host programs. Because of its positioning in relation to the high performance main storage unit its size is transparent to the other programs of the system since it overflows automatically into the main storage unit. It also has multiple interfaces which provide a more simple matching of the bank widths and transfer rates of the rest of the scientific processor.

Local store for scientific vector processor

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Anoka, MN, United States of America

David J Tanglin