Intel Corporation

David J Shield

Michael J Allen

Stephen Anthony Fischer

Richard D Pashley

Joseph D Schutz

Charles H Lucas

David R Gray

Patrick P Gelsinger

Babak Sabi

Stephen F Sullivan

Stuart T Hopkins

Gregory K Crain

Derek L Davis

Gustay Laub, Iii

Gustav Laub, Iii

A CMOS microprocessor chip includes an on-chip single-poly EPROM that is process compatible with the CMOS process used to manufacture the microprocessor. The EPROM is used to store manufacturing and contract related data such as serial number, customer, and process related data such as wafer number test results, binning data, etc. This provides important information for quality and reliability control. The EPROM is also used to control selection of optional microprocessor features such as speed governing, pin-out and I/O bus interface configuration. A third use is for trimming of critical circuit elements and for cache redundancy fault control.

Microprocessor having single poly-silicon EPROM memory for programmably

A method and apparatus for fast electronic self-destruction of a CMOS integrated circuit. The present invention electrically destroys devices containing semiconductor components, securing the components from inspection by detecting the initiation of an attempt to inspect the component and, responsive thereto, electrically destroying the component. In some embodiments of the present invention, a switcheable pad having a destruct state and an operating state is connected to a well or to the substrate of the semiconductor device. When in destruct state, the switcheable pad drives the voltage of the well or substrate to a voltage that induces latch-up of the semiconductor device, allowing very large currents to flow through active or passive elements fabricated on the surface of the semiconductor device. In some embodiments, a fusible link having an open state and a closed state connects the switcheable pad to one power supply, so that when the switcheable pad is switched to the destruct state, the fusible link opens, thereby redirecting current through the parasitic PNPN junction of the semiconductor device, thus inducing large latch-up currents through the cell's fusible link and causing it to open, thus destroying the ability of that logic element to function or process data.

Method and apparatus for fast self-destruction of a CMOS integrated

A CMOS microprocessor chip includes an on-chip single-poly EPROM that is process-compatible with the CMOS process used to manufacture the microprocessor. The EPROM is used to store manufacturing and contract related data such as serial number, customer, and process related data such as wafer number test results, binning data, etc. This provides important information for quality and reliability control. The EPROM is also used to control selection of optional microprocessor features such as speed governing, pin-out and I/O bus interface configuration. A third use is for trimming of critical circuit elements and for cache redundancy fault control.

Apparatus for reducing the operating voltage for an integrated circuit. The integrated circuit includes a first input conductor coupled to an operating voltage and a second input conductor coupled to system ground. A logic circuit having a positive rail and a negative rail is coupled between the first input conductor and the second input conductor such that the positive rail is coupled to the first input conductor via a first impedance and the negative rail is coupled to the second input conductor via a second impedance. A first sense conductor is connected to said positive rail between said first impedance and said logic circuit for sensing the voltage at the positive rail. In this manner, the potential at the positive rail of the logic device is accurately sensed. The integrated circuit may be incorporated in a remote sensing system wherein a remote sense conductor of the power supply is coupled to sense the potential at the positive rail. The power supply may thus adjust its output voltage in response to the voltage sensed at the logic circuit.

Method and apparatus for reducing the nominal operating voltage supplied

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El Dorado Hills, CA, United States of America

David J Shield