Texas Instruments Corporation

Sirenza Microdevices, Inc.

David J Seymour

Randall E Lehmann

David D Heston

Stuart M Jacobsen

Darius Lammont Crenshaw

Tsen-Hwang Lin

Charles L Goldsmith

Charles M Rhoads

Lily Y Pang

Frank J Morris

Gailon E Brehm

Billy Powers, Jr

Timothy M Gittemeier

Bill R Norvell

Bradley M Kanack

Randy L Cochran

The present invention provides a method and product-by-method of integrating a bias resistor in circuit with a bottom electrode of a micro-electromechanical switch on a silicon substrate. The resistor and bottom electrode are formed simultaneously by first sequentially depositing a layer of a resistor material (), a hard mask material () and a metal material () on a silicon substrate forming a stack. The bottom electrode and resistor lengths are subsequently patterned and etched () followed by a second etching () process to remove the hard mask and metal materials from the defined resistor length. Finally, in a preferred embodiment, the bottom electrode and resistor structure is encapsulated with a layer of dielectric which is patterned and etched () to correspond to the defined bottom electrode and resistor.

Micro-electromechanical switch fabricated by simultaneous formation of a resistor and bottom electrode

An apparatus comprising a first circuit and a second circuit. The first circuit may be configured to generate an intermediate signal in response to an input signal. The second circuit may be configured to generate a plurality of output signals in response to the intermediate signal. Each of the output signals may be (i) an amplified versions of the input signal and (ii) isolated between each of the other output signals.

Multi-output amplifier with isolation between outputs

The present invention provides a method and product-by-method of integrating a bias resistor in circuit with a bottom electrode of a micro-electromechanical switch on a silicon substrate. The resistor and bottom electrode are formed simultaneously by first sequentially depositing a layer of a resistor material ( ), a hard mask material ( ) and a metal material ( ) on a silicon substrate forming a stack. The bottom electrode and resistor lengths are subsequently patterned and etched ( ) followed by a second etching ( ) process to remove the hard mask and metal materials from the defined resistor length. Finally, in a preferred embodiment, the bottom electrode and resistor structure is encapsulated with a layer of dielectric which is patterned and etched ( ) to correspond to the defined bottom electrode and resistor.

An apparatus comprising an amplifier and a circuit. The amplifier may be configured to amplify an input signal. The circuit may be configured to (i) control the amplifier, (ii) compensate for non-linear characteristics of the amplifier, (iii) increase third-order intercept (TOI) and (iv) increase the output 1 dB compression point (P1 dB).

TOI and power compression bias network

Micromechanical microwave switches with both ohmic and capacitive coupling of rf lines and integration in multiple throw switches useful in microwave arrays.

Micromechanical microwave switching

A semiconductor device which includes a channel region of predetermined conductivity type having a pair of opposing surfaces (11 or 33) , a control element of opposite conductivity type disposed on one of the opposing surfaces (13 or 31) and a pair of spaced apart electrodes (17, 19 or 35, 37) disposed over the other of the opposing surfaces. The control element and channel region form a pn junction therebetween. An electrically insulating layer (15) can be disposed between the spaced apart electrodes (17, 19) and the channel region (11) in a high frequency embodiment.

Back gate FET microwave switch

Monolithic gallium arsenide limiters (30) formed of p-i-n diodes (32, 34) that are distributed devices between conductors of coplanar waveguide sections (40, 42, 44) are disclosed. The diode doped regions underlie the coplanar conductors and the diode intrinsic region underlies the coplanar waveguide gap. The grounded coplanar segments connect to a backside ground through vias (74).

Monolithic p-i-n diode limiter

This invention provides a switched limiter with variable attenuation designed with monolithic GaAs p-i-n diodes. Greater than 30 dB of small-signal variable attenuation is achieved at X band frequencies, with a minimum insertion loss of 0.5 dB. The variable attenuation switched limiter provides 15 dB of isolation to a +30 dBm input signal. Under bias conditions that result in variable attenuation the variable attenuation switched limiter input impedance remains matched. When used as a passive limiter, 7 dB of limiting has been achieved for a +30 dBm input signal at 10 GHz.

Matched variable attenuation switched limiter

A monolithic low noise variable gain amplifier with series feedback includes a dual gate field effect transistor (DGFET) having a common source FET and a common gate FET with scaled gate widths and/or an interelectrode matching element connected to ground through a capacitor positioned between the two gates for reducing the minimum noise figure of the common gate FET and establishing the output load for the common source FET, and an inductive series feedback line for connecting the common source FET to ground. The amount of series feedback between the source and ground of the DGFET as well as the appropriate output load obtained through gate width scaling are selected to make the conjugate input impedance equal to the optimum impedance for a simultaneous noise match and power match.

Dual-gate, field-effect transistor low noise amplifier

A monolithic amplifier having a common-gate input stage with a device transconductance which is higher than required for input match, and a load impedance presented to the common-gate stage which is not conjugate matched. The present invention teaches a common-gate configuration using an FET with higher transconductance and a higher output load impedance. Over narrower bandwidths, excellent input match is thus obtained with noise figures at least as good as those obtained with the common-source approach. This combination of noise figure and input match is achieved in a compact monolithic structure.

Growing community of inventors

Plano, TX, United States of America

David J Seymour