Intel Corporation

Digital Equipment Corporation

Other

Hewlett-packard Development Company, L.p.

Compaq Computer Corporation, Inc.

David J Sager

Darrell D Boggs

Michael D Upton

Glenn J Hinton

Amit A Merchant

Simon C Steely, Jr

Thomas D Fletcher

James D Allen

Ian A Young

Edward Thomas Grochowski

Joel S Emer

Douglas M Carmean

Ruchira Sasanka

Vivek Tiwari

David W Burns

David J Ayers

Michael C Adler

Francis X McKeen

Jayaram Bobba

Per H Hammarlund

Shlomo Raikin

Jeffrey J Cook

Suresh Srinivas

Raj K Ramanujan

Robert P Nix

P Geoffrey Lowney

Youfeng Wu

Francis X Mckeen

Stephan Jourdan

Koichi Yamada

Ron Gabor

Joseph Nuzman

Ronak Singhal

Robert F Krick

Tin-Fook Ngai

Chan W Lee

Arvind Krishnaswamy

Ho-Seop Kim

Karol F Menezes

David B Fite, Jr

Omar M Shaikh

William A Samaras

Leeor Peled

Howard Chen

Abhinav Das

Thomas F Toll

Andrew D Ingraham

Jason A Domer

Leon D Hesch

Zeev Sperber

Feng Chen

Stanislav Shwartsman

Eric A Sprangle

Adi Yoaz

Peter J Bannon

Nicholas G Samra

Ross Segelken

Jason M Agron

Michael Haertel

James Benjamin Saxe

Alexander P Henstrom

David W Clift

Paul C Wade

Evgeni Krimer

William B Noyce

Jay C Stickney

Ori Lempel

Anne S Valiton

Andrey Varpahovsky

Jeffery J Cook

P Geoffrey Lowny

Jeffrey L Bell

Omer Golz

Darrell D Buggs

Systems, apparatuses, and methods for a hardware and software system to automatically decompose a program into multiple parallel threads are described. In some embodiments, the systems and apparatuses execute a method of original code decomposition and/or generated thread execution.

Systems, apparatuses, and methods for a hardware and software system to automatically decompose a program to multiple parallel threads

A mechanism for tracking the control flow of instructions in an application and performing one or more optimizations of a processing device, based on the control flow of the instructions in the application, is disclosed. Control flow data is generated to indicate the control flow of blocks of instructions in the application. The control flow data may include annotations that indicate whether optimizations may be performed for different blocks of instructions. The control flow data may also be used to track the execution of the instructions to determine whether an instruction in a block of instructions is assigned to a thread, a process, and/or an execution core of a processor, and to determine whether errors have occurred during the execution of the instructions.

Using control flow data structures to direct and track instruction execution

Systems, apparatuses, and methods for a hardware and software system to automatically decompose a program into multiple parallel threads are described. For example, a method according to one embodiment comprises: analyzing a single-threaded region of executing program code, the analysis including identifying dependencies within the single-threaded region; determining portions of the single-threaded region of executing program code which may be executed in parallel based on the analysis; assigning the portions to two or more parallel execution tracks; and executing the portions in parallel across the assigned execution tracks.

A processor including a first execution core section clocked to perform execution operations at a first clock frequency, and a second execution core section clocked to perform execution operations at a second clock frequency which is different than the first clock frequency. The second execution core section runs faster and includes a data cache and critical ALU functions, while the first execution core section includes latency-tolerant functions such as instruction fetch and decode units and non-critical ALU functions. The processor may further include an I/O ring which may be still slower than the first execution core section. Optionally, the first execution core section may include a third execution core section whose clock rate is between that of the first and second execution core sections. Clock multipliers/dividers may be used between the various sections to derive their clocks from a single source, such as the I/O clock.

Processor having execution core sections operating at different clock rates

Methods and apparatus relating to a hardware move elimination and/or next page prefetching are described. In some embodiments, a logic may provide hardware move eliminations based on stored data. In an embodiment, a next page prefetcher is disclosed. Other embodiments are also described and claimed.

Tracking mechanism coupled to retirement in reorder buffer for indicating sharing logical registers of physical register in record indexed by logical register

In a multi-threaded processor, thread priority variables are set up in memory. The actual assignment of thread priority is based on the expiration of a thread precedence counter. To further augment, the effectiveness of the thread precedence counters, starting counters are associated with each thread that serve as a multiplier for the value to be used in the thread precedence counter. The value in the starting counters are manipulated so as to prevent one thread from getting undue priority to the resources of the multi-threaded processor.

Method and apparatus for assigning thread priority in a processor or the like

Replay instruction morphing. One disclosed apparatus includes an execution unit to execute an instruction. A replay system replays an altered instruction if the execution unit executes the instruction erroneously.

Replay instruction morphing

A system for delivering power to a device in a specified voltage range is disclosed. The system includes a power delivery network, characterized by a response function, to deliver power to the device. A current computation unit stores values representing a sequence of current amplitudes drawn by the device on successive clock cycles, and provides them to a current to voltage computation unit. The current to voltage computation unit filters the current amplitudes according to coefficients derived from the response function to provide an estimate of the voltage seen by the device. Operation of the device is adjusted if the estimated voltage falls outside the specified range.

Mechanism for estimating and controlling di/dt-induced power supply voltage variations

Fusing a load micro-operation (uop) together with an arithmetic uop. Intra-instruction fusing can increase cache memory storage efficiency and computer instruction processing bandwidth within a microprocessor without incurring significant computer system cost. Uops are fused, stored in a cache memory, un-fused, executed in parallel, and retired in order to optimized cost and performance.

Fusing load and alu operations

Growing community of inventors

Portland, OR, United States of America

David J Sager