Cisco Technology, Inc.

Skhynix Inc.

Sk Hynix Memory Solutions Inc.

Cortina Systems Corporation

David J Pignatelli

Eldad Perahia

Bretton Lee Douglas

Fan Zhang

David Sheldon Stephenson

June Lee

Yu Cai

Ender Ayanoglu

Chenrong Xiong

Ozgur Gurbuz

Brian Donald Hart

Aman Bhatia

HyungSeok Kim

Paul C P Dankoski

Vincent Knowles Jones, Iv

Naveen Kumar

Johnny A Lam

Philip J Ryan

Santanu Sinha

Michael Scott Allison

Milind Paranjpe

Uri Parker

David S Stophenson

Alan Carr

A memory system and operating method thereof includes a semiconductor memory device, and a memory controller controlling actions of the memory device. The memory controller contains a processor executing instruction and programs stored in the memory controller, a memory characterizer characterizing the memory system, and generating an index decision table, an in-flight assessor assessing read command, and predicting a proposed error recovery action in accordance with the index decision table, and a selective decoder executing the proposed error recovery action.

Media quality aware ECC decoding method selection to reduce data access latency

A memory device includes a plurality of memory blocks, each block with multiple memory cells. Each memory block has an address and a block read threshold. The plurality of memory blocks is partitioned into clusters based on block read thresholds. The memory device also has a look-up table for storing information associating each cluster of memory blocks with a corresponding cluster read threshold. The look-up table further includes cluster boundaries defined in values of device status parameters. The memory device is configured to receive a read command to read a memory block with a read address and identify a cluster for the memory block with the read address. The memory device is also configured to select a cluster read threshold for the identified cluster from the look-up table, and use the selected cluster read threshold to perform a read operation of the memory block.

Read threshold optimization in flash memories

Disclosed are techniques for selecting one or more reference voltages for performing one or more operations on a memory cell based on a determined layer of a three-dimensional memory construct to which the memory cell belongs. The one or more operations can include read or write operations. The memory cell can be a flash memory cell.

Layer-based memory controller optimizations for three dimensional memory constructs

A flash memory management method and apparatus provides for the separation of the command and data paths so that communication paths may be used more efficiently, taking account of the characteristics of NAND FLASH circuits where the times to read, write and erase data differ substantially. A unique sequence identifier is assigned to a write command and associated data and association of the data and commands are validated prior to writing to the memory by comparing the unique sequence numbers of the data and command prior to executing the command. This comparison is performed after the data and command have traversed the communication paths.

Hardware integrity verification

A memory system includes a plurality of memory channels, each of the plurality of memory channels includes a plurality of memory dies and a die processor, each of the plurality of memory dies includes a plurality of memory blocks; and a memory controller including a monarch processor, coupled to the plurality of memory channels, wherein the die processor on each of the plurality of memory channels is configured in parallel to process to find last written data within at least a predetermined block of the plurality of memory dies; and provide information regarding the last written data to the monarch processor, the monarch processor determines which boot record to be used to identify firmware images based on the information.

Memory system and method for accelerating boot time

Techniques for codeword decoding are described. In an example, a system accesses information about a block of a storage device of the system. The block includes data lines and redundant lines. The data lines are available to store data and include a bad data line that is unreliable for data storage. The redundant lines include a redundant line that replaces the bad data line, and a free redundant line that remains available after replacement of all bad data lines from the data lines. The information includes an identifier of the bad data line and an identifier of the free redundant line. The system accesses a codeword stored in the block. A portion of the codeword is stored in the free redundant line. The system decodes the codeword based on the identifier of the bad data line and the identifier of the free redundant line.

Redundant bytes utilization in error correction code

Methods for decoding information stored on a memory may include performing a hard read at an initial threshold and determining a first distribution percentage, performing a hard read at a subsequent threshold and determining a second distribution percentage, generating a log-likelihood ratio (LLR) based on the hard reads performed at the initial and subsequent thresholds, and based on the first and second distribution percentages, and soft decoding the information based on the generated LLR.

Incremental LLR generation for flash memories

An apparatus of a memory system and an operating method thereof includes a plurality of memory devices; and a controller coupled with the plurality of memory devices, configured to determine a range of read reference voltages having a plurality of read reference voltages, the read reference voltages achieving a minimal rBER; calculate an optimal read reference voltage in accordance with at least the range of read reference voltages; achieve a rBER in accordance with at least the optimal read reference voltage; and execute error correction process with at least the optimal read reference voltage.

Memory system of optimal read reference voltage and operating method thereof

Disclosed are techniques for determining a threshold number of read operations on memory depending on one or more conditions of the memory. If a number of read operations for the memory meets the threshold number of read operations, a read reclaim operation can be performed to preserve data stored therein.

Techniques for dynamically determining performance of read reclaim operations

An apparatus of a memory system and an operating method thereof includes a plurality of memory devices; and a controller coupled to the plurality of memory devices, wherein the controller is configured to perform a symmetric OVS read with at least an initial read threshold, and create a symmetric read result; perform an asymmetric OVS read with at least the initial read threshold, and create an asymmetric read result; adjust the initial read threshold according to at least the symmetric read result and asymmetric read result, and create an optimal read threshold; and execute data recovery process with the optimal read threshold.

Memory system with read threshold estimation and operating method thereof

A method of controller optimization utilizing over-sampling read (OSR) in a memory device includes performing a first internal read at a predetermined threshold level and transferring the first internal read measurement to the controller, performing a second internal read in a range that is between the predetermined threshold level plus a first predetermined value and the predetermined threshold level minus a second predetermined value, and determining whether a cell level falls in the range and transferring the second internal read measurement to the controller.

Methods of system optimization by over-sampling read

Memory systems may include a logical block address (LBA) space divided into a number of zones, a counter associated with each zone, each counter suitable for incrementing a count value when a read is performed on an LBA in the zone with which the counter is associated, and a controller suitable for calculating a temperature of each zone based on the count values of the counters, sorting the zones according to the calculated temperature, combining the zones into a number of superzones based on the sorting, and splitting the number of superzones into the number of zones into which the LBA space was divided.

Data temperature profiling by smart counter

A method of managing a non-volatile memory system is described where data elements stored in a buffer are characterized by attributes and a write data tag is created for the data elements. A plurality of write data tag queues is maintained so that different data attributes may be applied as sorting criteria when the data elements are formed into pages for storage in the non-volatile memory. The memory system may be organized as a RAID system and a write data tag queue may be associated with a specific RAID group such that the data pages may be written from a buffer to the non-volatile memory in accordance with the results of sorting each write data queue. The data elements stored in the buffer may be received from a user, or be read from the non-volatile memory during the performance of system overhead operations.

Write cache sorting

Methods of determining distributions may include performing a number of hard reads, performing a number of background reads at a frequency based on the number of hard reads, and estimating a conditional probability density of a cell voltage based on the hard reads and the background reads.

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Saratoga, CA, United States of America

David J Pignatelli