Intel Corporation

Sk Hynix Nand Product Solutions Corp.

David J Pelster

Xin Guo

Yogesh B Wakchaure

Aliasgar S Madraswala

Mark Anthony Golez

Neelesh Vemula

David B Carlton

Donia Sebastian

Feng Zhu

Sarvesh Varakabe Gangadhar

Eric L Hoffman

Paul D Ruby

Yu Du

Mark Anthony Sumabat Golez

Pranav Kalavade

Peng T Li

Myron Loewen

Curtis A Gittens

Brennan A Watt

Ryan J Norton

Vivek Angoth

MarkAnthony Golez

Bhargavi Govindarajan

Ali Khakifirooz

Henry C Chu

Shantanu R Rajwade

Neal R Mielke

Ye Zhang

William Anthony Harper

Sagar Upadhyay

Gamil A Cain

Robert Frickey

Kyung Jean Yoon

Robert E Frickey

Joseph F Doller

Darshan Mallapur Vishwanath

Sagar S Sidhpura

David M Jones

David G Dreyer

Naga Kiranmayee Upadhyayula

Varsha Regulapati

Daniel R Mcleran

Nathan Koch

Teena Sebastian

Archana Rajagopal

Justin R Dayacap

Jing-Jing Li

Mark Anthony S Golez

Sudhakar Ayyasamy

Systems and methods are provided for dynamically changing the operating clock frequency of a circuit. Control circuitry determines a first workload value for a circuit operating at a first clock frequency. Control circuitry then detect a second workload value for the circuit, which is less than the first workload value. When the control circuitry detects the second workload value, the control circuitry calculates a second clock frequency which is greater than the first clock frequency. The control circuitry then causes the circuit to operate at the second clock frequency.

Methods and systems to dynamically improve low task storage depth latency in a solid-state drive device

An embodiment of an electronic apparatus may include one or more substrates, and a controller coupled to the one or more substrates, the controller including circuitry to control access to NAND-based storage media that includes a plurality of NAND devices, determine if a current workload for a particular NAND device of the plurality of NAND devices is a random write workload, and, if so determined, disable a program suspend operation for only the particular NAND device. Other embodiments are disclosed and claimed.

Dynamic program suspend disable for random write SSD workload

This application is directed to managing garbage collection using a plurality of queues of memory bands of a memory system. The memory system obtains a request to organize data stored in a plurality of memory bands of the memory system, and each memory band has a data validity level. In response to the request, the memory system generates the plurality of queues of memory bands based on the data validity levels of the plurality of memory bands, and the plurality of queues correspond to a plurality of non-overlapping validity level ranges. The plurality of memory bands are assigned into a subset of queues based on the data validity levels of the plurality of memory bands. The memory systemallocates a first memory bandwidth among the subset of queues, and implements garbage collection operations on the subset of queues in parallel using respective portions of the first memory bandwidth.

Free space and input/output stability management for non-uniform workloads

A method performed by a solid state drive is described. The method includes, on a channel that internally couples a controller of the solid state drive to a storage device of the solid state drive, sending write data for a program operation to be performed by one of the storage device's logical units in separate chunks over the channel. The method also includes inserting higher priority traffic items of other logical units of the storage device in between the separate chunks.

Solid state drive with multiplexed internal channel access during program data transfers

Mechanisms for improving read command processing times in a solid-state drive (SSD) are provided, the mechanisms comprising: determining a workload type of an SSD; in response to determining that the workload type is a pure read workload type: determining at least one command size into which an original background write is to be split-up using at least one hardware processor; and splitting-up the background write into a plurality of split background writes, each having one of the determined at least one command size. In some embodiments, the at least one command size accounts for a page of the physical medium of the SSD. In some embodiments, the at least one command size includes at least two different sizes. In some embodiments, the mechanisms further comprise combining two or more split background writes. In some embodiments, the original background write is split-up before being placed in a channel queue.

System method for improving read command process times in solid-state drives (SSD) by having processor split-up background writes based on determined command size

A method and controller for operating a memory system in communication with a host. The method and controller logically arrange a sequence of reclaim sub-groups within a memory device. The method and controller process the reclaim sub-groups according to the sequence to control the memory device to perform garbage collection on the reclaim sub-groups in the memory device. In the sequence, the reclaim sub-groups are processed during the garbage collection such that at least one re-ordered data sequence in the sequence of the reclaim sub-groups being processed has re-ordered valid data that is not clumped.

Validity distribution for performance uniformity

Mechanisms for controlling background wear leveling are provided, including: increasing a first counter; comparing the first counter to a first threshold; and in response to the first counter meeting the first threshold: decreasing the first counter by a value of the first threshold; and triggering background wear leveling. In some embodiments, the first counter is increased in response to receiving a write trigger. In some embodiments, the first threshold is based upon a page size and a number of planes of physical media of an SSD. In some embodiments, the mechanisms further comprise: incrementing a second counter in response to receiving a host write trigger; comparing the second counter to a second threshold; and in response to the second counter meeting the second threshold, decreasing the second counter by the second threshold, wherein the increasing the first counter is performed in response to the second counter meeting the second threshold.

Systems, methods, and media for controlling background wear leveling in solid-state drives

Mechanisms for reducing the impact of drive parameter writes on solid state drive (SSD) performance are provided, the methods including: saving one or more SSD drive parameters of an SSD to volatile memory of the SSD using an SSD controller; detecting a power-loss condition in the SSD; and copying the one or more SSD drive parameters from the volatile memory of the SSD to non-volatile memory of the SSD. In some embodiments, the SSD is a NAND SSD. In some embodiments, the one or more SSD drive parameters include one or more of: a drive health parameter, a drive internal statistic, drive thermal information, drive debug information, a number of host and non-volatile memory read and writes, media error handling data, temperature and throttle information, and firmware download information. In some embodiments, the volatile memory is one or more of: random-access memory and dynamic random-access memory.

Systems, methods, and media for reducing the impact of drive parameter writes on solid state drive performance

An apparatus is described. The apparatus includes a memory chip having logic circuitry to suspend application of an erasure voltage, wherein, respective responses of the erasure voltage to a decision to suspend the application of the erasure voltage depend on where the erasure voltage is along its waveform.

Solid state drive (SSD) with in-flight erasure iteration suspension

A data structure is maintained for performing a program operation that is allowed to be suspended to perform reads in a NAND device, where the data structure indicates a plurality of tiers, where each tier of the plurality of tiers has a number of allowed suspends of the program operation while executing in the tier, and where a sum of the number of allowed suspends for all tiers of the plurality of tiers equals a maximum allowed number of suspends of the program operation. In response to performing a resume of the program operation, after performing a read following a suspend of the program operation, a determination is made of a tier of the plurality of tiers for the program operation and a subsequent suspend of the program operation is performed only after a measure of progress of the program operation has been exceeded in the determined tier.

Method, system, and apparatus for multi-tiered progressive memory program operation suspend and resume

A solid state drive (SSD) includes a nonvolatile memory array and a cache memory. The nonvolatile memory array has an encrypted integrated memory buffer (IMB) space. The cache memory has a decrypted copy of the IMB and an encrypted backup copy of the IMB. In power loss recovery (PLR) after a power loss imminent (PLI) event, the SSD can determine whether to recover the unencrypted copy of the IMB or the backup encrypted copy. The backup encrypted copy can reduce the risk of loss of data in the IMB in the event that multiple PLI events occur and a corrupted copy of the IMB is used to overwrite the IMB in the nonvolatile memory during a previous PLR.

Data loss prevention for integrated memory buffer of a self encrypting drive

Independent multi-plane commands for non-volatile memory devices are described. In one example, a three-dimensional (3D) NAND memory device includes 3D NAND dies, each die including multiple planes of memory cells. The device includes input/output (I/O) circuitry to receive multiple commands from a host, each of the received commands to access one of the planes. The device includes logic (which can be implemented with, for example, an ASIC controller, firmware, or both) to queue the commands in separate queues for each of the planes based on a target plane of each of the commands. The logic issues the commands to their target planes independent of other planes' status, and tracks completion status of the commands independently for each plane.

Independent NAND memory operations by plane

An example apparatus includes a non-volatile memory including a first memory having a first write rate and a second memory having a second write rate, the first write rate greater than the second write rate An example controller is to determine, based on a ratio, a first portion of the data to be written to the first memory, and a second portion of the data to be written to the second memory type, the second portion of the data not included in the first portion of the data.

Methods and apparatus to configure performance of a solid state drive based on host write bandwidth

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Longmont, CO, United States of America

David J Pelster