Intel Corporation

David J Nedwek

Howard A Wilson

Greg Dermer

Steve Nugent

A method for configuring a plurality of configurable components within a computer system. The method includes the step of asserting a RESET signal for all of the configurable components. The RESET signal is asserted by a diagnostic processor within the system. The components each respond with an ERROR # signal which provides an indication to the diagnostic processor that the component is in an inactive state. After a predetermined number of clock signals the diagnostic processor configures a first component, then a second component and so forth and so on, until all of the components are configured. After all of the components are configured, the diagnostic processor deasserts the RESET signal for the first component, then deasserts the RESET signal for the second component and so forth and so on, until all of the RESET signals have been deasserted. Each component deasserts the ERROR # signal upon the deassertion of the RESET signal. The diagnostic processor allows normal operation to occur upon the deassertion of all the ERROR # signals.

Method for initializing an array of configurable components

A system for enabling processor cells in a high speed multi-processor environment to communicate with each other so as to resolve synchronization problems caused by propagation and other delays inherent in such an environment. The invention is for systems for which the data delay is both bounded and fixed wherein the maximum data delay is part of the system specifications and all cells operate at the same frequency. Data is transmitted along with a clock to allow the receiving cell to properly recover the data regardless of the state of the receiver's internal clocks. Both the transmitting cell and the receiving cell are operating at the same frequency (because their clock signals are derived from the same master oscillator), but the range of delays associated with the transmission of data places no bounds on the allowable phase difference between the received data's clock and the receiver's internal clock state.

Self-synchronizing data queues

A circuit that includes a self-biased differential amplifier a level restore circuit. The output of the differential amplifier is coupled to the source pins of a p type transistor and an n type transistor. The output of the differential amplifier is further coupled to a first inverter circuit that provides feedback to the gates of the p and n type transistors. The first inverter also further amplifies the output voltage of the differential amplifier. When the differential amplifier outputs a high voltage, the p transistor attempts to drain the output and pull the output voltage down. When the differential amplifier begins switching from a high voltage to a low voltage, the p transistor accelerates the voltage swing and decreases the propagation delay of the buffer circuit. Likewise, when the differential amplifier swings from a low voltage to a high voltage, the n type transistor reduces the propagation delay of the voltage swing.

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Beaverton, OR, United States of America

David J Nedwek