Tektronix, Inc.

David J McKinney

Grigory Kogan

Eric P Etheridge

Spiro Sassalos

A logic analyzer uses a single tapped delay line and a single array of sampling cells for high speed digital signal acquisition, by controlling both edges of a substantially 50% duty cycle clock signal to drive a delay line buffer chain. The chain operates continuously; there being no need for interruptions for precharge intervals. Thus, the need for a second delay line buffer chain is eliminated.

Track-and-hold signal generator having a time-aligned clock

A first comparison circuit compares an internally generated clock signal with a reference signal and produces a first error signal in response to timing differences between rising edges of the clock signal and the reference signal. A second comparison circuit compares the internally generated clock signal with the reference signal and produces a second error signal in response to timing differences between falling edges of the clock signal and the reference signal. The first and second error signals are applied to control inputs of a phase shifter chain to control delay in each stage to reduce the timing error with respect to each edge.

Clock signal generator for a logic analyzer controlled to lock both

A programmable delay circuit with a simplified structure conserves parts and provides for simplified programmability. In this structure, N delay stages (1-N) each include delay elements (10,26, . . . ,80) that produce delay times that are related as powers of two and are connected by two-input multiplexers (12,22, . . . ,82). The two-input multiplexers select between the input and output of the delay element in their stage, and are collectively controlled by N-bits of delay selection signals that are connected so that less significant bits control multiplexers associated with delay elements producing shorter delays and more significant bits control multiplexers associated with delay elements producing longer delays in a monotonic correspondence. The resulting structure conserves parts and produces an overall delay time that is directly proportional to the binary value used to control the multiplexers. Alternative embodiments are disclosed in which delay elements are related as powers of an arbitrary base number Y instead of two, but this embodiment does not provide all possible delay values and the delay provided is not proportional to the value of the binary bits used for control.

Simplified structure for programmable delays

An accurate delay generator circuit for delaying the rising and falling edge of an input signal includes: a current switch having an input for receiving the input signal, first and second current inputs, and a current output; a p-channel transistor coupled to the first current input of the current switch; a first threshold voltage generator coupled to the gate of the p-channel transistor for generating a voltage equal to twice a p-channel threshold voltage with respect to VDD; an n-channel transistor coupled to the second current input of the current switch; a second threshold voltage generator coupled to the gate of the n-channel transistor for generating a voltage equal to twice an n-channel thresold voltage with respect to ground; a capacitor coupled to the output of the current switch; and an output inverter stage coupled to the output of the current switch for providing the delayed input signal. The threshold voltage generators provide constant voltages that are independent of VDD and ground from the gate to source of the p-channel and n-channel transistors respectively. The constant gate to source voltages produce relatively constant charge and discharge currents to the capacitor that in turn produce a relatively constant delay for both the rising and falling edge of the input signal. In addition, the configuration of the present invention compensates for errors in the value of the delay produced by variations in semiconductor processing parameters.

Growing community of inventors

Beaverton, OR, United States of America

David J McKinney