Micron Technology Incorporated

David J McElroy

Stephen L Casper

Eugene H Cloud

Leonard Forbes

Kie Y Ahn

Paul A Farrar

Luan C Tran

Alan R Reinberg

Joseph E Geusic

Voltage coupling/decoupling devices are provided within DRAM devices for improving the bias sensing of sense amplifiers and thus the refresh performance. The voltage coupling/decoupling devices couple or decouple bias voltage from corresponding digit lines coupled to the sense amplifiers. By coupling and decoupling voltage from the digit lines, the time interval between refresh operations can be increased.

Methods for bias sensing in DRAM sense amplifiers through voltage-coupling/decoupling devices

Bias sensing in DRAM sense amplifiers through voltage-coupling/decoupling device

Bias sensing in sense amplifiers through a voltage-coupling/decoupling device

Imaging arrays typically include thousands or millions of photodetectors that convert sensed light into corresponding electric signals, which are ultimately converted into digital image signals for recording or viewing. One problem with conventional imaging arrays concerns faulty photodetectors, which produce erroneous image signals that ultimately degrade the quality of resulting images. Accordingly, the present inventors devised new imaging arrays including redundant photodetectors to compensate for faulty ones. One exemplary embodiment includes photodetectors that are substantially smaller than conventional photodetectors and that are arranged into two or more groups, with the photodetectors in each group coupled to produce a single group image signal. If the group image signal for a group falls below some threshold level indicative of a defective or malfunctioning photodetector, the group image signal is amplified to compensate for the loss.

Compensation methods and systems for imaging detectors

Redundant imaging systems

Bias sensing in DRAM sense amplifiers through coupling and decoupling device

Bias sensing in DRAM sense amplifiers

Imaging arrays are electronic devices that sense light and output electrical signals representative of the sensed light. An imaging array comprises thousands or millions of photodetectors that convert sensed light into corresponding electric signals, which are ultimately converted into digital image signals for recording or viewing. One problem with conventional imaging arrays concerns defective or malfunctioning photodetectors. Defective photodetectors typically result in erroneous image signals that ultimately degrade the quality of resulting images. Accordingly, the present inventors devised new imaging arrays including redundant photodetectors to compensate for defective photodetectors. One exemplary embodiment includes one or more photodetectors that are substantially smaller than conventional photodetectors, for example about 10 or 25 square microns. The smaller-than-conventional photodetectors are arranged into two or more groups, with each group having two or more photodetectors coupled to produce a single group image signal. If the group image signal for a group falls below some threshold level indicative of a defective or malfunctioning photodetector, the group image signal is amplified to compensate for the loss.

Imaging system having redundant pixel groupings

Structures and methods involving n-channel flash memories with an ultrathin tunnel oxide thickness, have been provided. Both the write and erase operations are performed by tunneling. According to the teachings of the present invention, the n-channel flash memory cell with thin tunnel oxides will operate on a dynamic basis. The stored data can be refreshed every few seconds as necessary. However, the write and erase operations will however now be orders of magnitude faster than traditional n-channel flash memory and the cell provides a large gain. The present invention further provides structures and methods for n-channel floating gate transistors which avoid n-channel threshold voltage shifts and achieve source side tunneling erase. The n-channel memory cell structure includes a floating gate separated from a channel region by an oxide layer of less than 50 Angstroms (&angst;). According to the teachings of the present invention, the floating gate is adapted to hold a charge of the order of 10 Coulombs at for at least 1.0 second at 85 degrees Celsius. The method includes applying a potential of less than 3.0 Volts across the floating gate oxide which is less than 50 Angstroms, in order to add or remove a charge from a floating gate. The method further includes reading the n-channel memory cell by applying a potential to a control gate of the n-channel memory cell of less than 1.0 Volt.

Dynamic flash memory cells with ultra thin tunnel oxides

Structures and methods involving n-channel flash memories with an ultrathin tunnel oxide thickness, have been provided. Both the write and erase operations are performed by tunneling. According to the teachings of the present invention, the n-channel flash memory cell with thin tunnel oxides will operate on a dynamic basis. The stored data can be refreshed every few seconds as necessary. However, the write and erase operations will however now be orders of magnitude faster than traditional n-channel flash memory and the cell provides a large gain. The present invention further provides structures and methods for n-channel floating gate transistors which avoid n-channel threshold voltage shifts and achieve source side tunneling erase. The n-channel memory cell structure includes a floating gate separated from a channel region by an oxide layer of less than 50 Angstroms (&angst;). According to the teachings of the present invention, the floating gate is adapted to hold a charge of the order of 10,Coulombs at for at least 1.0 second at 85 degrees Celsius. The method includes applying a potential of less than 3.0 Volts across the floating gate oxide which is less than 50 Angstroms, in order to add or remove a charge from a floating gate. The method further includes reading the n-channel memory cell by applying a potential to a control gate of the n-channel memory cell of less than 1.0 Volt.

Dynamic flash memory cells with ultrathin tunnel oxides

A CAM device that utilizes a portion of a desired content as a row address is provided. A row in a CAM memory array is accessed using the row address portion of the desired content. The remaining portion of the desired content is used as a key data tag for comparison with content stored within memory locations of the addressed row. This way, the CAM device does not have to sequentially access each row in the memory array to locate memory cells having the desired content. The CAM can comprise a standard DRAM memory array, sense amplifiers and compare logic located in the sense amplifiers. Alternatively, the CAM device can comprise a standard SRAM memory array and associated compare logic. By accessing the CAM device using a portion of the desired content as a row address, the CAM device can perform a high speed search while also reducing the complexity of the CAM circuitry.

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Owens Cross Roads, AL, United States of America

David J McElroy