Compaq Computer Corporation, Inc.

David J Maguire

James R Edwards

Dwight D Riley

Patrick Lee Ferguson

Gregory N Santos

Robert A Lester

Jeffrey C Stevens

Hung Q Le

Maria L Melo

Khaldoun Alzien

Richard S Lin

Christopher C Wanner

David J Delisle

Robert C Elliott

William C Hallowell

James R Reif

Gregory Pero

Mayu Si

An apparatus handles long latency interrupt signals in a computer which posts I/O write operations. The apparatus includes a posting buffer for posting write operations and circuitry for ensuring that End-of-Interrupt (EOI) write operations (and other interrupt controller directed I/0 operations) are properly synchronized to prevent false interrupts from reaching the processor. Upon receipt of the EOI write operation, the apparatus verifies that the posting buffer is empty before it imposes a pre-determined delay to ensure sufficient time for the cleared the interrupt signal to be transmitted over the interrupt serial bus. Next, the apparatus checks the interrupt serial bus for activities. If the interrupt serial bus is idle, the EOI write operation is issued to the interrupt controller. Alternatively, the apparatus waits until the serial bus becomes inactive for two back-to-back cycles before allowing the EOI write operation to be issued to the interrupt controller. The back-to-back wait requirement prevents false interrupts from being generated in the event that the cleared interrupt may have missed its transmission window over the current interrupt serial bus cycle, or the event that the cleared interrupt was delayed by any interrupt serial bus transmission latencies.

Long latency interrupt handling and input/output write posting

A computer system includes a bus bridge which provides an interface between a processor bus, a main memory and a peripheral bus such as a PCI or AGP bus. When a cycle to memory is initiated on the PCI or AGP bus by a peripheral device, a snoop control circuit of the bus bridge arbitrates for the processor bus to initiate a snoop cycle which corresponds to the line being accessed by the peripheral device. In addition to performing a snoop for the current line being accessed, the snoop control circuit further advantageously runs a speculative snoop cycle for the next sequential line. By performing a speculative snoop cycle on the CPU bus to the next line address, latencies associated with subsequent accesses to memory by the peripheral device may be reduced if the device performs a subsequent sequential access. Furthermore, since the bus bridge performs multiple snoop cycles per arbitration cycle (e.g., multiple snoop cycles are effectuated with only one BPRI_assertion), bandwidth on the CPU bus may be optimized since a CPU bus arbitration cycle may be avoided for the snoop to the sequential line address.

Computer system and method employing speculative snooping for optimizing performance

A bridge logic unit provides an interface between a microprocessor coupled to a processor bus, a main memory coupled to memory bus, and a peripheral device coupled to a peripheral bus, such as a PCI bus. To maintain coherency, the bridge logic unit disables write posting in certain specific situations, and flushes posted write transactions before allowing certain read requests to be serviced. More specifically, in one embodiment when a PCI device performs a read to main memory, which may be implemented within the bridge as delayed read, the bus bridge blocks CPU to PCI transactions and flushes any posted CPU to PCI transactions pending in the bridge. The bus bridge enables CPU to PCI posting after the pending CPU to PCI transactions have been flushed and after the snoop phase of a snoop cycle corresponding to the memory read operation completes. In a further embodiment, prior to performing a PCI read cycle on behalf of a read cycle initiated by the microprocessor, the bus bridge determines whether any PCI to memory transactions are pending in the PCI slave transient write buffer. If any posted write transactions reside in the PCI slave transient write buffer, the bus bridge retries the read cycle on the processor bus and blocks any subsequent posting of write transactions to memory from the PCI bus. When the pending PCI to memory transactions have been flushed from the PCI slave transient write buffer, and the microprocessor reattempts the read, the read cycle is initiated on the PCI bus. At this point, PCI to memory write posting is re-enabled.

System and method for maintaining coherency and improving performance in a bus bridge supporting write posting operations

The present invention relates to a system and method for shadowing data of a first register and a second register of a computer system that share a common address. When a bus agent runs a write operation to the register address, retry logic of a first bridge circuit retries the write operation and masks access by the bus agent to the bus. Retry bus master logic reruns the write operation, in response to which the second bridge circuit subtractively decodes the rerun write operation and transfers the data to the second register. The bus agent is then allowed to retry the initial write operation, in response to which the first bridge circuit positively decodes the retried write operation and transfers the data to the first register. Thus, coherency is preserved between the first and second registers.

Bus system for shadowing registers

A computer is provided having a bus interface unit coupled between a CPU bus and a mezzanine bus, or PCI bus. The bus interface unit includes a plurality of input buffers which can be selectively connected and disconnected in a dynamic fashion according to active and inactive signals forwarded thereto. Signals forwarded to the bus interface unit from the CPU are classified according to the transaction phase of CPU bus activity. If signals associated with one particular transaction phase are active, then input buffers attributed to signals of other transaction phases can be deactivated. It is preferred that input buffers associated with signals of a request and arbitration phase be maintained active and coupled to power regardless of the present transaction phase unless the computer enters a powered down mode, such as sleep, idle or standby.

Device and method for dynamically reducing power consumption within input buffers of a bus interface unit

A method for hot docking and hot undocking a portable computer and a docking station. The portable computer and docking station are physically coupled via a shared PCI bus and an expansion connector. Varying length pins in the expansion connector generate docking and undocking handshaking signals used by microcontrollers in the portable computer and docking station. The portable computer and docking station are functionally connected via low onresistance switches located in the portable computer. Following a docking event, closure of the switches connects the portion of the shared PCI bus in the docking station with the PCI bus in the portable computer. When the switches are open, the PCI busses are functionally isolated. Both the portable computer and the docking station also include a local arbiter for arbitrating and granting bus control requests from devices coupled to the shared PCI bus. These local arbiters may be placed into an idled state by either the operating system (through system BIOS) or by the microcontrollers. The arbiters are idled during docking and undocking events in order to inhibit bus cycles on the PCI bus, thereby preventing cycles from being lost. Following completion of a hot docking or undocking event, Plug-and-Play system reconfiguration is carried out so that all system resources may be recognized and properly utilized by the operating system.

Computer system implementing hot docking and undocking capabilities by

The present invention relates to a low latency serial bus system for shadowing registers between first and second digital devices. Either the first device or the second device may initiate a data transfer cycle on the serial bus when data in a shadowed register of that device has changed. The data transfer cycle includes a first frame where data is transferred from the first device to the second device and a second frame where data is transferred from the second device to the first device. The devices do not initiate a subsequent data transfer cycle for changed data if the changed data can be transferred in the current data transfer cycle.

Serial bus system for shadowing registers

A computer system having separate, yet compatible DMA controllers on a bus. Each DMA controller for controlling at least one DMA channel, each DMA controller having an independent set of registers for performing DMA operations and a configuration register for indicating channel status and designation. A DMA master for compatibly communicating with a processor and for initializing and communicating with the multiple DMA controllers.

Interfacing direct memory access devices to a non-ISA bus

An arbitration scheme for a computer system having multiple arbiters for arbitrating access to a plurality of buses. In the preferred embodiment, a computer system is divided into a detachable laptop portion and an expansion base unit coupled through a shared PCI bus. Each of the two portions of the computer system includes separate PCI arbitration circuitry for arbitrating requests for the PCI bus from potential PCI and ISA bus masters. Included within the laptop portion of the computer system is a top level arbiter that determines whether the PCI arbiter in the laptop or expansion base unit has access to the PCI bus. Either PCI arbiter normally must receive a grant from the top level arbiter before it runs a cycle. While the laptop computer is docked, the top level arbiter selects between the PCI arbiters on an essentially time multiplexed basis. While the expansion base and laptop computer are undocked, the top level arbiter grants bus access to the laptop PCI arbiter.

Circuit for handling distributed arbitration in a computer system having

An apparatus handles long latency interrupt signals in a computer which posts I/O write operations. The apparatus includes a posting buffer for posting write operations and circuitry for ensuring that End-of-Interrupt (EOI) write operations (and other interrupt controller directed I/O operations) are properly synchronized to prevent false interrupts from reaching the processor. Upon receipt of the EOI write operation, the apparatus verifies that the posting buffer is empty before it imposes a pre-determined delay to ensure sufficient time for the cleared the interrupt signal to be transmitted over the interrupt serial bus. Next, the apparatus checks the interrupt serial bus for activities. If the interrupt serial bus is idle, the EOI write operation is issued to the interrupt controller. Alternatively, the apparatus waits until the serial bus becomes inactive for two back-to-back cycles before allowing the EOI write operation to be issued to the interrupt controller. The back-to-back wait requirement prevents false interrupts from being generated in the event that the cleared interrupt may have missed its transmission window over the current interrupt serial bus cycle, or the event that the cleared interrupt was delayed by any interrupt serial bus transmission latencies.

A method for hot docking and hot undocking a portable computer and a docking station. The portable computer and docking station are physically coupled via a shared PCI bus and an expansion connector. Varying length pins in the expansion connector generate docking and undocking handshaking signals used by microcontrollers in the portable computer and docking station. The portable computer and docking station are functionally connected via low on-resistance switches located in the portable computer. Following a docking event, closure of the switches connects the portion of the shared PCI bus in the docking station with the PCI bus in the portable computer. When the switches are open, the PCI busses are functionally isolated. Both the portable computer and the docking station also include a local arbiter for arbitrating and granting bus control requests from devices coupled to the shared PCI bus. These local arbiters may be placed into an idled state by either the operating system (through system BIOS) or by the microcontrollers. The arbiters are idled during docking and undocking events in order to inhibit bus cycles on the PCI bus, thereby preventing cycles from being lost. Following completion of a hot docking or undocking event, Plug-and-Play system reconfiguration is carried out so that all system resources may be recognized and properly utilized by the operating system.

System incorporating hot docking and undocking capabilities without

A computer system having an expansion base for docking a portable portion of the computer system includes a bridge circuit for adaptively decoding addresses on a bus based on the docking status. Both the expansion base and the portable portion include the bridge circuit for passing cycles from a peripheral component interconnect (PCI) bus to an industry standard architecture (ISA) bus. The bridge includes internal devices and configuration registers for controlling the decoding. Bus cycles intended for internal devices and external devices connected to each respective ISA bus of the bridge circuits are positively decoded. Cycles not positively decoded and claimed are subtractively decoded by one of the bridge circuits depending on the docking status.

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Spring, TX, United States of America

David J Maguire