Hewlett Packard Enterprise Development LP

Hewlett-packard Development Company, L.p.

Compaq Information Technologies Group, L.p.

David J Koenen

Charles L Hudson

Robert Teisberg

Sompong Paul Olarig

Alan L Goodrum

Suhas Shivanna

Michael L Witkowski

Mike Chuang

Patrick Schoeller

Chai S Heng

An example device includes a processor; a first interface port forming a first datalink to a core network device via a first interconnect device; and a second interface port forming a second datalink to the core network device via a second interconnect device, the first and second datalinks being redundant connections of a link aggregation group (LAG) including a plurality of multiplexed connections within a single network media. The processor is to: remove the first interconnect device while maintaining the second datalink; update firmware of the first interconnect device upon receiving a first indication that the first interconnect device has stopped receiving or transmitting data; and reestablish the redundant connections of the first interconnect device upon receiving a second indication that the first interconnect device has been added back to the LAG. The first and second indications include indications of states in each connection of the multiplexed connections.

Firmware update of an interconnect device

Providing power to a server includes a switch with power sourcing equipment (PSE) and a server with a network interface controller (NIC) the PSE to transfer power to the NIC of the server via a network cable to change configuration settings prior to the server booting from a stand-by mode.

Providing power to a server

An example device includes a processor coupled to a network and a memory coupled to the processor. The memory includes computer code for causing the processor to establish a secure connection between a manageability application and an interconnect device, the interconnect device being in communication with a newly connected networked device; and securely communicate, from the manageability application to the interconnect device, temporary login information for the networked device.

Secure login information

This invention provides the ability to significantly lower the power consumed by a group of Ethernet links when organized in a Link Aggregation Group. When the server or switch senses low bandwidth utilization across multiple links in the group, it will negotiate the transition of un-necessary links to a lower power state. When the bandwidth requirements increases, the algorithm will quickly re-establish links and distribute the Ethernet traffic across the multiple links when necessary.

Method for ethernet power savings on link aggregated groups

A technique includes network booting a physical machine coupled to a network by a link aggregation group. The technique includes selectively disabling ports of the physical machine associated with the link aggregation group in connection with the network booting until a driver of an operating system to group the ports together is installed on the physical machine.

Network booting a machine coupled to the network by a link aggregation group

A technique for improving performance in a multi-processor system by reducing access latency by correlating processor, node and memory allocation. Specifically, a Process/Thread Scheduler is modified such that system mapping and node proximity tables may be referenced to help determine processor assignments for ready-to-run processes/threads. Processors are chosen to minimize access latency. Further, the Page Fault Handler is modified such that free memory pages are assigned to a process based partially on the proximity of the memory with respect to the processor requesting memory allocation.

Method and apparatus for optimizing performance in a multi-processing system

A method and apparatus for distributing power to a plurality of computers in a network. A power management system including a feed-back mechanism, is employed to monitor power consumptions of the plurality of computers. Should the overall power consumption reach a threshold, the power management system instructs the microprocessors in the plurality of computers to enter into a lower power state, such as a sleep state, for a certain duration, thus lowering overall power.

Progressive CPU sleep state duty cycle to limit peak power of multiple computers on shared power distribution unit

A memory controller capable of supporting heterogeneous memory configurations enables seamless communications between a bus and memory modules having different characteristics. Thus, owners of computer systems need no longer replace entire memory arrays to take advantage of new memory modules; some memory modules may be upgraded to a new type while other memory modules of an older type remain. The memory controller receives memory requests from multiple processors and bus masters, identifies a memory module and memory access parameters for each request, accesses the memory and returns the resulting data (during a read request) or stores the data (during a write request). In some systems, the memory controller of the present invention is a two-tier memory controller system having a first memory controller coupled to the bus and to the second tier of memory controllers or RAM personality modules that translate between the first memory controller and a particular type of memory module. Typically, between the tiers a protocol is used which is representative of a typical clocked synchronous dynamic random access memory (SDRAM), although another protocol could be used. From the perspective of the processor bus or host bus coupled to the front end of the first memory controller, the entire memory controller system behaves as a single memory controller. From the perspective of memory, the back end of the RAM personality module is seen as a memory controller designed specifically to be configured for that memory type. Consequently, although the front end of the RAM personality module can be standardized across the system, compatible with the back end of the first memory controller, and in most embodiments of the present invention, the back end of the RAM personality module differs among the controller modules in the second tier, according to the variety of the memory modules in the memory system.

Method and apparatus for supporting heterogeneous memory in computer systems

A heat dissipating apparatus for use on a heat generating electric component inside a computer comprises an interposer mounted on the heat generating electric component and a heat absorbing member including a heat absorber, a bracing member, and a spring biasing said heat absorber toward the bracing member. The heat absorbing member is moveable between a first position in which the interposer is compressed between the heat absorber and the bracing member and a second position in which the interposer is not compressed between the heat absorber and the bracing member.

Growing community of inventors

Austin, TX, United States of America

David J Koenen