International Computers Limited

David J Hunt

Stewart F Reddaway

A sequence generator for producing a sequence of binary numbers, comprises a counter, a priority encoder which encodes the contents of the counter, a memory addressed by the output of the encoder, an output register, and a logic circuit for modifying the contents of the output register as specified by the output from the memory. The generated sequence can readily be modified by changing the contents of the memory. The flexibility of the generator can be increased further by using as the counter a count register which is incremented by values from a further memory also addressed by the output of the encoder.

Sequence generator

A run-length decoder arranged to produce output signals in groups, each group being output in parallel. The decoder includes a position register which indicates the position, within a group, of the latest transition between signal values. The contents of this register are added to the incoming run-length code so as to calculate the number of groups to be output before the next transition and the position within the group of that next transition. The calculated number of groups is then output and a transition is introduced into the calculated position in the next group to be output.

Apparatus for decoding run-length encoded data

An array processor in which each sub-array of processing elements has a group of check-bit processing elements associated with it. The check-code processing elements have north-south interconnections, but have no east-west connections. Instead, the northernmost element of each group is connected diagonally to the southernmost element of the neighboring group, so as to permit serial transfer of check codes, over the north-south connections and the diagonal connections, between adjacent groups in the east-west direction.

Array processor

A data processing system is disclosed consisting of a plurality of data processing elements and parity processing elements. The parity processing elements hold parity bits for checking the contents of the internal registers and internal stores of the data processing elements and perform substantially the same operations on the parity bits as the data processing elements perform on the data. However, some of these operations may invalidate the parity bits. In particular, the carry result from an addition operation is not always valid. A parity valid logic circuit is therefore provided to generate a signal which indicates whether the parity bits from all the parity processing elements are valid, and hence whether the parity check performed using these parity bits is valid.

Data processing system with error checking

An array processor is described consisting of a plurality of modules connected together in rows and columns. Each module has at least one special terminal which, as well as providing a connection for transfer of data between adjacent modules, also provides an output which is combined with similar signals from the other modules in the same row, to form a row response signal. Alternate modules in each row are rotated by 180.degree. with respect to each other, so that the special terminals on adjacent modules are connected in pairs. This reduces the complexity of the circuits for forming the row response signals.

A binary adder circuit which, in response to a mode selection signal, is forced to operate as if two of its inputs were equal, irrespective of the actual value of those inputs. In this condition, the circuit acts effectively as a connector, coupling two of its inputs direct to the sum and carry outputs. The invention is useful in a circuit arrangement for performing adding and shifting operations.

Binary adder circuit

A binary adder has a switching circuit connected to one of its inputs. When activated by a mode selection signal, the switching circuit forces two of the adder inputs to receive the same input signal. In this condition the adder acts effectively as a connector, coupling two of its inputs direct to the sum and carry outputs. The invention is useful in an array processor, for performing additions and shifting operations.

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Hitchin, United Kingdom

David J Hunt