International Business Machines Corporation

Globalfoundries Inc.

David J Hill

Stephen Peter Ayotte

Timothy M Sullivan

Glen E Richard

Heather M Truax

John Thomas Kinnear, Jr

Timothy Harrison Daubenspeck

Jeffrey D Gilbert

Ronald Lee Mendelson

Kristen L Holverson

Christina Marie Pepi

Methods and structures provide an electrostatic discharge (ESD) indicator including an electric field sensitive material configured to undergo a specific color change in response to an electric field. An exposure of the structure to an ESD can be visually determined via the specific color change of the ESD indicator.

Visually detecting electrostatic discharge events

Aspects of the disclosure provide a method of inhibiting crack propagation in a silicon wafer. In one embodiment, a method of repairing an imperfection on a surface of a semiconductor device is disclosed. The method includes: screening for imperfections on a surface of a silicon wafer of a semiconductor device; and in response to at least one imperfection on the surface of the silicon wafer, depositing a material on the surface of the silicon wafer.

Inhibiting propagation of imperfections in semiconductor devices

Stacked multichip packages and methods of making multichip packages. A method includes using a boat having different depth openings corresponding to the length of column interconnections of the completed multichip package and masks to place proper length columns in the corresponding depth openings; placing an integrated circuit chip on the boat and attaching exposed upper ends of the columns to respective chip pads of the integrated circuit using a first solder reflow process and attaching a preformed package substrate integrated circuit chip stack to the integrated circuit and attached columns using a second solder reflow process.

Stacked multi-chip package and method of making same

Aspects of the present invention relate to a controlled collapse chip connection (C4) structures. Various embodiments include a method of forming a controlled collapse chip connection (C4) structure. The method can include: providing a precursor structure including: a substrate, a dielectric over the substrate, the dielectric including a plurality of trenches exposing a portion of the substrate, and a metal layer over the dielectric and the portion of the substrate in each of the plurality of trenches, forming a resist layer over the metal layer, forming a rigid liner over a surface of the resist layer and the metal layer, and forming solder over the rigid liner between portions of the resist layer.

Controlled collapse chip connection (C4) structure and methods of forming

A heat sink for cooling a heat-generating device includes a base and a cooling section coupled thereto for cooling the device. The cooling section includes a plurality of flow tubes, each flow tube having an inlet, an outlet, and a bounding wall that defines a closed fluid flow path from the inlet to the outlet. Each of the flow tubes includes a central axis that is substantially parallel to a reference plane of the heat-generating device. The flow tubes may be arranged in a layered stack and include a bounding wall that has a thickness that decreases with increasing distance in the layered stack. The flow tubes may also include a cross-sectional area that decreases with increasing distance in the layered stack. Furthermore, the bounding wall of the flow tubes may have a non-planar configuration in a direction generally parallel to the central axis.

Low profile heat sink for semiconductor devices

Methods for making, and structures so made for producing integrated circuit (IC) chip packages without forming micro solder balls. In one embodiment, a method may include placing a solid grid made from an organic material between the IC chip and the substrate. The grid provides a physical barrier between each of a plurality of Controlled Collapse Chip Connections, and thereby prevents the formation of micro solder balls between them, thus improving chip performance and reliability.

Production of integrated circuit chip packages prohibiting formation of micro solder balls

A rectangular-shaped controlled collapse chip connection (C) is described. In one embodiment, there is a semiconductor chip package that comprises a semiconductor chip package substrate and a semiconductor chip having a plurality of rectangular-shaped Ccontacts attached thereto that connect the semiconductor chip to the semiconductor chip package substrate. The plurality of rectangular-shaped Ccontacts are arranged along a surface of the semiconductor chip in an orientation that extends radially from a center of the surface of the semiconductor chip.

Growing community of inventors

Richmond, VT, United States of America

David J Hill