Micron Technology Incorporated

Other

David J Hansen

Mark E Jost

Steven M McDonald

Corey D Brown

Pouran Rissmaney

Don We Evans

Anne F Mickelson

A semiconductor processing method of forming integrated circuitry on a semiconductor wafer includes, a) forming at least two discrete wafer alignment patterns on the wafer, the two discrete alignment patterns having respective series of elevation steps provided therein; and b) while fabricating integrated circuitry elsewhere on the wafer, processing a first portion of at least one of the alignment patterns differently from a second portion of the one alignment pattern to render the first portion to be different from the second portion in the one alignment pattern. Such preferably superimposes a secondary step, most preferably of the same degree, over only a portion of the elevation steps in at least one of the wafer alignment patterns. Further, a semiconductor processing method of forming integrated circuitry on a semiconductor wafer includes, i) forming at least two discrete wafer alignment patterns on the wafer, the two discrete alignment patterns having respective series of elevation steps provided therein; and ii) while fabricating integrated circuitry elsewhere on the wafer, processing one of the alignment patterns differently from the other to render the one alignment pattern to be different from the other alignment pattern.

Semiconductor wafer, wafer alignment patterns and method of forming wafer alignment patterns

Semiconductor wafer,wafer alignment patterns and method of forming wafer alignment patterns

A semiconductor processing method of forming integrated circuitry on a semiconductor wafer includes, a) forming at least two discrete wafer alignment patterns on the wafer, the two discrete alignment patterns having respective-series of elevation steps provided therein; and b) while fabricating integrated circuitry elsewhere on the wafer, processing a first portion of at least one of the alignment patterns differently from a second portion of the one alignment pattern to render the first portion to be different from the second portion in the one alignment pattern. Such preferably superimposes a secondary step, most preferably of the same degree, over only a portion of the elevation steps in at least one of the wafer alignment patterns. Further, a semiconductor processing method of forming integrated circuitry on a semiconductor wafer includes, i) forming at least two discrete wafer alignment patterns on the wafer, the two discrete alignment patterns having respective series of elevation steps provided therein; and ii) while fabricating integrated circuitry elsewhere on the wafer, processing one of the alignment patterns differently from the other to render the one alignment pattern to be different from the other alignment pattern.

Semiconductor wafer, wafer alignment patterns and method of forming

Method of forming wafer alignment patterns

A tanning apparatus includes a plurality of tubular lamp housings releasably joined together in an electrical series relationship for tanning either an erect or recumbent person. Lamp housings, walls, and power cords are easily attachable and detachable for adjusting the configuration of the apparatus. Each lamp housing includes an ultraviolet lamp, ballast, and igniter. The lamp housing further includes a front panel which allows access to the lamp for replacement while protecting a user from injury in case a lamp bursts during use. The front panel is transparent, allowing ultraviolet rays to be transmitted toward a user. Reflective surfaces within the lamp housings and on the interior wall surfaces further contribute to efficient tanning. A frame is provided to support the apparatus above a recumbent user. The lamp housings may also be vertically positioned to surround and tan an erect user. Following use, the apparatus may be rolled into a compact bundle and secured by straps for transport or storage.

Home tanning apparatus

A semiconductor processing method of forming integrated cicuitry on a semiconductor wafer includes, a) forming at least two discrete wafer alignment patterns on the wafer, the two discrete alignment patterns having respective-series of elevation steps provided therein; and b) while fabricating integrated circuitry elsewhere on the wafer, processing a first portion of at least one of the alignment patterns differently from a second portion of the one alignment pattern to render the first portion to be different from the second portion in the one alignment pattern. Such preferably superimposes a secondary step, most preferably of the same degree, over only a portion of the elevation steps in at least one of the wafer alignment patterns. Further, a semiconductor processing method of forming integrated circuitry on a semiconductor wafer includes, i) forming at least two discrete wafer alignment patterns on the wafer, the two discrete alignment patterns having respective series of elevation steps provided therein; and ii) while fabricating integrated circuitry elsewhere on the wafer, processing one of the alignment patterns differently from the other to render the one alignment pattern to be different from the other alignment pattern.

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Boise, ID, United States of America

David J Hansen