Motorola Corporation

David J Halchin

John M Golio

Lawrence S Klingbeil, Jr

James G Gilbert

Charles E Weitzel

Robert C Turner

Monte G Miller

A field effect transistor (10) has an active layer (16) formed in a substrate (12). A gate (20) is disposed on an elevated platform (18) formed from the active layer (16). The elevated platform (18) raises the bottom surface (21) of the gate (20) relative to the top surface (34, 36) of the active region (13) on either side of the gate (20). A fabrication method for the transistor (10) forms the elevated platform (18) by etching the active region surface (44) on both sides of the gate (20) so that the bottom surface (21) of the gate (20) is elevated relative to the top surface (34) of the surrounding active region (13). The gate (20) itself and/or a patterned photoresist layer (116) may be used as a mask for performing this etch.

Method for fabricating an elevated-gate field effect transistor

A method executed by a computer for performing numerical optimization of arbitrary functions in a computer model using parallel processors (10, 12, 14). The method initializes (20) each processor with an initial estimate of the parameter value to be optimized. The initial estimate is evaluated (22) in each processor to determine a solution. A best estimate of the parameter value from the result in each processor is selected (24), and one or more of the parallel processors with the best estimate is set to run in gradient mode while the remaining processors run in random mode (26). The estimates of the parameter value from the processors running in random mode is evaluated until a local minimum is obtained from the processor running in gradient mode (28). The process is repeated until an optimal solution is found (34).

Optimization method using parallel processors

Elevated-gate field effect transistor structure and fabrication method

A diode protected semiconductor device appropriate for the output of a radio frequency amplifier, which can withstand substantial power reflection due to output impedance mismatch, is provided. The device may be implemented monolithically, in the form of a field effect transistor (FET) (14) having a back to back diode pair (17) connecting the drain (18) to the source (19). The FET comprises multiple transistor portions (28) coupled together. The diode pair comprises corresponding diode pair portions (37) coupled together. The configuration provides easy integration of the diode pair (17) into typical FET structures.

Diode protected semiconductor device

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Chandler, AZ, United States of America

David J Halchin