Sun Microsystems, Inc.

Oracle America, Inc.

Intel Corporation

Oracle International Corporation

David J Greenhill

Robert Paul Masleid

Sudhakar Bobba

Georgios K Konstadinidis

Joseph Raymond Siegel

Hanh-Phuc Le

Miriam G Blatt

Claude R Gauthier

Pradeep R Trivedi

Sean R Atsatt

Tyler J Thorp

Ravi Prakash Gutala

Scott J Weber

Sebastian Turullols

Aravind Raghavendra Dasu

Sorin Iacobovici

Philip Arnold Ferolito

Gin S Yee

Jun Pin Tan

Daniel Lawrence Leibholz

Sanjiv Kapil

Junji Sugisawa

Kathirgamar Aingaran

Sundari S Mitra

Poonacha P Kongetira

Weiran Kong

Curtis Roger McAllister

Ronald J Melanson

Chakra R Srivatsa

King Cheung Yen

Bernard Ho

James Tran

Bijoy Kalloor

Thomas R Caron

Shanker Bhagvat

Ban-Pak Wong

Vidyasagar Ganesan

Larry Kan

An integrated circuit device may cache configuration data to enable rapid configuration from fabric cache memory. The integrated circuit device may include programmable logic fabric having configuration memory and programmable logic elements controlled by the configuration memory, and sector-aligned memory apart from the programmable logic fabric. A first sector of the configuration memory may be programmed with first configuration data. The sector-aligned memory may include a first sector of sector-aligned memory that may cache the first configuration data while the configuration memory is programmed with the first configuration data a first time. A second sector of sector-aligned memory may cache second configuration data for a second sector of the configuration memory in parallel while the first sector of sector-aligned memory caches the first configuration data for the first sector of the configuration memory.

Configuration or data caching for programmable logic device

Disclosed is a digital voltage regulator system and method for mitigating voltage droop in an integrated circuit. If an unacceptable voltage droop is detected, the digital voltage regulator may take action to allow the power supply voltage to recover. A digital voltage regulator in accordance with embodiments discussed herein detects voltage droop by comparing a power supply voltage measurement with a threshold voltage. The threshold voltage may be calibrated based on power supply voltage measurements taken while the integrated circuit is operating.

Microprocessor performance and power optimization through self calibrated inductive voltage droop monitoring and correction

A digital voltage regulator including a dual rail delay chain having large size, feed forward cross-coupled inverters that interconnect the two rails. Stages of the delay chain include a dual-ended output that provides a data signal and a substantially simultaneous data complement signal to a flip-flop component associated with a sampling circuit. In use, the enhanced resolution delay chain and the reduced metastability window flop-flop increase the precision of the digital voltage regulator.

Minimal bubble voltage regulator

An integrated circuit that includes a digitally controlled oscillator (DCO) that adjusts a clock frequency of a critical path of the integrated circuit based on the variations in a power-supply voltage of the DCO and the critical path is described. This DCO may be included in a feedback control loop that includes a frequency-locked loop (FLL), and which determines an average clock frequency of the critical path based on a reference frequency. Furthermore, the DCO may have a selectable delay characteristic that specifies a delay sensitivity of the DCO as a function of the power-supply voltage, thereby approximately matching a manufactured delay characteristic of the critical path. Additionally, for variations in the power-supply voltage having frequencies greater than a resonance frequency associated with a chip package of the integrated circuit, adjustments of the clock frequency may be proportional to the variations in the power-supply voltage and the selectable delay characteristic.

Power-supply noise suppression using a frequency-locked loop

The described embodiments include a system that modulates the width of a high-speed link. The system includes a transmitter circuit coupled to a high-speed link that includes N serial lanes. During operation, while using a first number of lanes to transmit frames on the high-speed link, the transmitter circuit determines a second number of lanes to be used to transmit frames on the high-speed link based on a bandwidth demand on the high-speed link. The transmitter circuit then sends an indicator of the second number of lanes to a receiver on the high-speed link. Upon receiving an error-free acknowledgment of the indicator from the receiver, starting from a predetermined frame, the transmitter circuit transmits subsequent frames on the high-speed link using the second number of lanes.

Method and apparatus for modulating the width of a high-speed link

A dual rail delay chain having cross-coupled inverters that interconnect the two rails. Delay chain embodiments include cross-coupled inverters that are part of a feed forward signal path between the two rails and are of a larger size than inverters associated with the two rails. The large size feed forward cross-coupled inverters contribute to an enhanced resolution of the delay chain.

Fine grain timing

A pulse generator circuit. The pulse generator circuit includes a precharge circuit coupled to receive a clock signal alternating between a first logic level and a second logic level, a storage circuit having a storage node, wherein the precharge circuit is configured to precharge the storage node when the clock signal is at the first logic level, a logic circuit having an output, a first input node coupled to receive the clock signal, and a second input node coupled to the storage node and configured to produce a pulse at the second logic level responsive to the clock signal transitioning to the second logic level, and a discharge circuit configured to discharge the storage node at a predetermined delay time subsequent to the clock signal transitioning to the second logic level, wherein the output of the logic circuit transitions to the first logic level responsive to discharging the storage node.

Precision pulse generator

A system includes an input device, an output device, a mechanical chassis, a printed circuit board, and a semiconductor device. The semiconductor device includes a mechanical package, and a semiconductor die. The semiconductor die includes a semiconductor layer, a plurality of metal layers, a clock distribution network that distributes a clock signal within the die, and an economy precision pulse generating circuit. The economy precision pulse generating circuit includes a pre-charge circuit, a gate-to-the-partial-jam-latch-keeper circuit, a partial-jam-latch-keeper circuit, and a pull-down-against-the-up-keeper circuit. A source clock signal is derived from the clock signal. The source clock signal is provided to a first input of a logical AND circuit, the pre-charge circuit, and the gate-to-the-partial-jam-latch-keeper circuit. A common storage node is connected to a second input of the logical AND circuit. The logical AND circuit outputs an output pulse. The output pulse is fed back to the pull-down-against-the-up-keeper circuit.

Economy precision pulse generator

An integrated circuit test system. The test system includes a controller and an integrated circuit coupled to a voltage source and a current monitor. The controller causes the voltage source to supply a voltage to the integrated circuit, receives a signal from the current monitor indicating a power dissipation of the integrated circuit, and causes the voltage source to reduce the voltage until the signal from the current monitor indicates the power dissipation of the integrated circuit is less than a predetermined threshold. The controller stores in the integrated circuit in a non-volatile storage register that is accessible via a subset of access pins, a value corresponding to the voltage supplied to the integrated circuit when the power dissipation of the integrated circuit is less than the predetermined threshold. The subset of access pins provides at least one function in addition to accessing the non-volatile storage register.

Method and apparatus for setting VDD on a per chip basis

A method for data analysis of power modeling for a microprocessor has been developed. The method takes multiple values of power data from a power modeling simulator and generates summary data to characterize the power data behavior. Summary data views include results characterizing behavior in a single cycle and behavior across multiple cycles. Data is viewed both at an absolute level to characterize total power and relative to previous levels to characterize power derivatives. Summary data is derived from power generated every cycle when running specific benchmark programs on the power simulator.

Data analysis techniques for dynamic power simulation of a CPU

A method for optimizing a register file hierarchy in a multithreaded processor. The method includes providing a register file hierarchy with a plurality of register file cells, associating the plurality of register file cells with respective threads when the processor is operating in a multithreaded mode and flattening the plurality of register file cells with a single thread when the processor is operating in a single threaded mode. The register file cells correspond to threads of the multithreaded processor.

Versatile register file design for a multi-threaded processor utilizing different modes and register windows

A capacitor structure in a semiconductor device is provided. The capacitor structure includes a first power rail on a topmost level of the semiconductor device, and a second power rail on the topmost level of the semiconductor device. The capacitor structure also includes a dielectric layer disposed over at least a portion of one of the first power rail and the second power rail. The capacitor structure further includes a conductive layer disposed over and between the first power rail and the second power rail where the conductive layer is in electrical contact with the power rail not having the dielectric layer, and the conductive layer is disposed over the dielectric layer.

Thin capacitive structure

A system and method is provided for scan control and observation of a logical circuit that does not halt the operation of the system clock. Thus, all dynamic circuits within the system continue to evaluate and precharge normally. Moreover, the traditional method of placing a multiplexer before the data input of a clocked storage element to perform scan control and observation is no longer required. Consequently, the system and method provide a more efficient manner in which to perform scan control and observation of a logical circuit.

Method for scan testing and clocking dynamic domino circuits in VLSI systems using level sensitive latches and edge triggered flip flops

A method for synchronizing a data signal and a clock signal has been developed. The method first generates two separate intermediate data signals. The intermediate data signals lag the input data signal. The separate durations of the two lagging signals are combined to form an output data signal that is synchronized with the system clock signal.

Method for synchronizing clock and data signals

A method for modeling the power behavior of a pipelined processor has been developed. The method uses a power model integrated into a cycle accurate simulator. To create the power model, design blocks of the processor are divided into sub-blocks. Power modeling equations for each sub-block are developed by collaboration between the sub-block circuit designer and the simulator developer, using activity information relevant to the sub-block that is available in the simulator model. Each equation is calculated multiple times with different sets of power parameters to represent varying power conditions. Every simulation cycle, sub-block power is summed to generate full-chip power for multiple power conditions.

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Portola Valley, CA, United States of America

David J Greenhill