Compaq Computer Corporation, Inc.

Other

Packard Bell Nec

David J Delisle

Hung Q Le

Lee Warren Atkinson

David J Maguire

Maria L Melo

Richard S Lin

James R Edwards

Kevin W Eyres

Robin T Castell

G Edward Newman

Saifuddin T Fakhruddin

Robert A Kohtz

Lloyd W Gauthier

Patrick R Cooper

Todd J Deschepper

Russ Wunderlich

A method for hot docking and hot undocking a portable computer and a docking station. The portable computer and docking station are physically coupled via a shared PCI bus and an expansion connector. Varying length pins in the expansion connector generate docking and undocking handshaking signals used by microcontrollers in the portable computer and docking station. The portable computer and docking station are functionally connected via low onresistance switches located in the portable computer. Following a docking event, closure of the switches connects the portion of the shared PCI bus in the docking station with the PCI bus in the portable computer. When the switches are open, the PCI busses are functionally isolated. Both the portable computer and the docking station also include a local arbiter for arbitrating and granting bus control requests from devices coupled to the shared PCI bus. These local arbiters may be placed into an idled state by either the operating system (through system BIOS) or by the microcontrollers. The arbiters are idled during docking and undocking events in order to inhibit bus cycles on the PCI bus, thereby preventing cycles from being lost. Following completion of a hot docking or undocking event, Plug-and-Play system reconfiguration is carried out so that all system resources may be recognized and properly utilized by the operating system.

Computer system implementing hot docking and undocking capabilities by

A computer system having a processor, a microcontroller, a flash ROM is provided with an address remapper for handling warm-boot events, and an arbiter for selectively assigning the ownership of the flash ROM to either the microprocessor or the microcontroller. The arbiter assigns the flash ROM initially to the microcontroller when power is initially provided to the system. After the flash ROM boots up and checks the integrity of the flash ROM and updates the content of the flash ROM with valid firmware if necessary, the microcontroller releases the flash ROM to the microprocessor to enable the computer system to proceed with the normal boot-up process. In this process, various system self tests are performed. Next, the microprocessor copies or shadows one or more portions of the flash ROM BIOS into a main memory array. After the shadow operation, the processor sets a remap bit to indicate that the ROM BIOS content has been copied into the main memory array. The setting of the remap bit enables the remapper to deflect accesses to the flash ROM. The restarting of the clock signal to the microcontroller to switch the ownership of the flash ROM back to the microcontroller. In the event that the microprocessor needs to regain access to the flash ROM contents, the microprocessor writes to the mailbox register of the arbiter to request access to the flash ROM. The microprocessor waits for a confirmation from the arbiter that the microcontroller is entering an idled mode. Next, the microprocessor halts the clock of the microcontroller. These events cause the microcontroller to float or tristate the signal lines going from the microcontroller to the flash ROM such that the microprocessor can drive the signal lines without any conflict potentials. In this manner, the microprocessor can still access the shared flash ROM after it has booted up. Thus, the system cost is reduced, the system reliability is enhanced, while the system accessibility to the flash ROM after the boot-up period is still preserved.

Flash ROM sharing between processor and microcontroller during booting

A computer system includes an I/O controller and a bridge logic device which transmit status data via a serial bus. The I/O controller comprises an embedded controller, a memory device, and a serial bus interface including a transceiver, a transmit register, and a receiver register. The bridge logic also includes a serial bus interface with a transceiver, a transmit register, and a receiver register. Data is transmitted from the transmit register of one device to the receive register of the other device. Although the serial bus protocol limits data transfers to eight-bit segments, the I/O controller and bridge logic transmit up to twenty-four different variables by encoding each transmitted byte into a data frame that includes a two-bit frame identifier and a six-bit data field. Further, one of the data frames transmitted by the I/O controller includes an acknowledge bit to indicate when a previous frame has been received from the bridge logic. The bridge logic only transmits new data if the I/O controller toggles the acknowledge bit and transmits the frame containing the toggled acknowledge bit to the bridge logic. The acknowledge bit prevents the South Bridge from overwriting previously transmitted data that has not yet been read from the receive register in the I/O controller.

Serial bus system for sending multiple frames of unique data

A method and apparatus for increasing system functionality through a predefined interface is disclosed. Signal lines which are not used or which are not used in certain modes are connected to an interconnection device instead of being connected to an interface wherein the output of the interconnection device is connected to the interface where such lines would have been connected. The interconnection device also has a set of inputs for receiving signals from a device providing the desired functionality. A controller chooses between the two sets of inputs to control what signal lines are connected to the predefined interface. Accordingly, during certain modes of operation, the added functionality from a device whose output is being switched into the interface can be supported. In one embodiment, speaker phone capability is provided for even though the predefined PCMCIA interface does not support such capability. The disclosed design continues to maintain capability with all systems adapted to be used with such predefined interface.

System for increasing functionality through a predefined interface by

A method for hot docking and hot undocking a portable computer and a docking station. The portable computer and docking station are physically coupled via a shared PCI bus and an expansion connector. Varying length pins in the expansion connector generate docking and undocking handshaking signals used by microcontrollers in the portable computer and docking station. The portable computer and docking station are functionally connected via low on-resistance switches located in the portable computer. Following a docking event, closure of the switches connects the portion of the shared PCI bus in the docking station with the PCI bus in the portable computer. When the switches are open, the PCI busses are functionally isolated. Both the portable computer and the docking station also include a local arbiter for arbitrating and granting bus control requests from devices coupled to the shared PCI bus. These local arbiters may be placed into an idled state by either the operating system (through system BIOS) or by the microcontrollers. The arbiters are idled during docking and undocking events in order to inhibit bus cycles on the PCI bus, thereby preventing cycles from being lost. Following completion of a hot docking or undocking event, Plug-and-Play system reconfiguration is carried out so that all system resources may be recognized and properly utilized by the operating system.

System incorporating hot docking and undocking capabilities without

In accordance with the invention, a computer system is provided with a flash read-only-memory (ROM), a microcontroller and a data port. The microcontroller initially owns the flash ROM. The microcontroller further has a separate ROM upon which it can execute boot-up instructions. After booting up, the microcontroller checks the flash ROM contents, preferably by performing a check-sum of the flash ROM contents. If the checksum of the flash ROM contents matches an expected value, the microcontroller releases ownership of the flash ROM to the computer system so that the computer system boots-up as normal. If the microcontroller determines that the flash ROM has become corrupted, the microcontroller accesses the data port and looks for a flash programming protocol. If the protocol is present at the data port, the microcontroller receives the data from the data port and programs the flash ROM accordingly. In this manner, the flash ROM can be updated to a good known state, even if the computer system is not able to boot up due to, among other things, the corruption of the flash ROM.

Computer system and method for replacing obsolete or corrupt boot code

In accordance with the invention, a computer system is provided with a processor, a flash ROM, a microcontroller and an arbiter for selectively assigning the ownership of the flash ROM to either the microprocessor or the microcontroller. The arbiter assigns the flash ROM initially to the microcontroller when it boots up. After checking the integrity of the flash ROM and updating the content of the flash ROM with valid software if necessary, the microcontroller releases the flash ROM to the microprocessor to enable the computer system to proceed with the normal boot-up process. In this process, various system self tests are performed. Next, the microprocessor shadows one or more portions of the flash ROM BIOS into a main memory array. After the processor successfully boots up, the processor releases the flash ROM back to the microcontroller by writing a command to a mailbox register in the arbiter which places the microcontroller in an idle mode and by restarting the clock generator of the microcontroller. The restarting of the clock signal to the microcontroller to switch the ownership of the flash ROM back to the microcontroller. In the event that the microprocessor needs to regain access to the flash ROM contents, the microprocessor writes to the mailbox register of the arbiter to request access to the flash ROM. The microprocessor waits for a confirmation from the arbiter that the microcontroller is entering an idled mode. Next, the microprocessor halts the clock of the microcontroller. These events cause the microcontroller to float or tristate the signal lines going from the microcontroller to the flash ROM such that the microprocessor can drive the signal lines without any conflict potentials. In this manner, the microprocessor can still access the shared flash ROM after it has booted up. Thus, the system cost is reduced, the system reliability is enhanced, while the system accessibility to the flash ROM after the boot-up period is still preserved.

Flash ROM sharing between a processor and a controller

Method and apparatus for functional expansion through predefined signal

A relatively fast system control processor, such as an Intel 8051, is substituted for an Intel 8042 microprocessor in a PC/AT type compatible personal computer. In one embodiment of the invention, a System Control Processor Interface (SCPI) is provided between the central processing unit (CPU) and the system control processor (SCP) to maintain compatibility with the PC/AT bus. The combination of the faster SCP and the SCPI interface improves the overall system performance. Control circuitry is also provided for setting the A20 signal relatively quickly to allow memory access above one megabyte. In an alternate embodiment of the invention, a Mouse Keyboard Interface (MKI) is provided. The MKI provides even quicker switching of the Gate A20 signal by eliminating the need to interrupt the SCP. The MKI also provides support for a type PS/2 mouse.

Growing community of inventors

Spring, TX, United States of America

David J Delisle