Intel Corporation

David J Cowperthwaite

Balaji Vembu

Altug Koker

Abhishek R Appu

Joydeep Ray

Kun Tian

Murali Ramadoss

David M Puffer

Prasoonkumar Surti

Subramaniam M Maiyuran

Ankur N Shah

Eric C Samson

Zhi Hu Wang

Niranjan L Cooray

Vasanth Ranganathan

Rajesh M Sankaran

Pattabhiraman K

Sameer Kp

Bryan R White

Satyeshwar Singh

Guei-Yuan Lueh

Adam T Lake

Aditya Navale

Philip R Lantz

Michael A Goldsmith

Tomas G Akenine-Moller

Changliang Wang

Bradford H Needham

Zhi Jun Wang

Brian T Lewis

Yunbiao Lin

Kiran S Panesar

Satyanantha Ramagopal Musunuri

Bradford H Needhan

Wei Zhang

Ravi L Sahita

Michael Apodaca

Peter L Doyle

Aravindh V Anantaraman

Jeffery S Boles

Brent E Insko

Hema Chand Nalluri

Arthur Hunter, Jr

Christopher J Cormack

Zhi Wang

Vidhya Krishnan

Vinay Phegade

Shanwei Cen

Zhenyu Wang

Kritika Bala

Matthew C Curfman

Kenneth Daxer

Kalyan Kondapally

Raman Srinivasan

Jonathan Bloomfield

Described herein is a partitionable graphics processor having multiple render front ends. The partitions of the graphics processor maintain render functionality when partitioned and enable fault isolation and independent multi-client rendering.

Multi-render partitioning

Embodiments described herein provide techniques to facilitate access to local memory of a graphics processor by a guest software domain. The guest software domain can access the local memory via an address translation system that includes a local memory translation table. In one embodiment, accessed and/or dirty bits are enabled in the local memory translation table, which may be used to accelerate the GPU local memory portion of VM Migration for a VM that includes a vGPU.

Local memory translation table accessed and dirty flags

Apparatus and method for implementing a virtual display. For example, one embodiment of a graphics processing apparatus comprises at least one configuration register to store framebuffer descriptor information for a first guest running on a first virtual machine (VM) in a virtualized execution environment of a host processor, the framebuffer descriptor information to indicate one or more display pipes assigned to the first guest; and execution circuitry to execute a first driver assigned to the first guest, the first guest to use the first driver to display a framebuffer in a plane associated with one of the display pipes in accordance with the framebuffer descriptor information.

Apparatus and method for a virtualized display

An apparatus and method are described for implementing memory management in a graphics processing system. For example, one embodiment of an apparatus comprises: a first plurality of graphics processing resources to execute graphics commands and process graphics data; a first memory management unit (MMU) to communicatively couple the first plurality of graphics processing resources to a system-level MMU to access a system memory; a second plurality of graphics processing resources to execute graphics commands and process graphics data; a second MMU to communicatively couple the second plurality of graphics processing resources to the first MMU; wherein the first MMU is configured as a master MMU having a direct connection to the system-level MMU and the second MMU comprises a slave MMU configured to send memory transactions to the first MMU, the first MMU either servicing a memory transaction or sending the memory transaction to the system-level MMU on behalf of the second MMU.

Apparatus and method for memory management in a graphics processing environment

Embodiments described herein provide techniques enable a graphics processor to continue processing operations during the reset of a compute unit that has experienced a hardware fault. Threads and associated context state for a faulted compute unit can be migrated to another compute unit of the graphics processor and the faulting compute unit can be reset while processing operations continue.

Compute cluster preemption within a general-purpose graphics processing unit

A virtual reality apparatus and method are described for tile-based rendering. For example, one embodiment of an apparatus comprises: a set of on-chip geometry buffers including a first buffer to store geometry data, and a set of pointer buffers to store pointers to the geometry data; a tile-based immediate mode rendering (TBIMR) module to perform tile-based immediate mode rendering using geometry data and pointers stored within the set of on-chip geometry buffers; spill circuitry to determine when the on-chip geometry buffers are over-subscribed and responsively spill additional geometry data and/or pointers to an off-chip memory; and a prefetcher to start prefetching the geometry data from the off-chip memory as space becomes available within the on-chip geometry buffers, the TBIMR module to perform tile-based immediate mode rendering using the geometry data prefetched from the off-chip memory.

Apparatus and method for optimized tile-based rendering

An apparatus and method for managing pipes and planes within a virtual graphics processing engine. For example, one embodiment of a graphics processing apparatus comprises: a graphics processor comprising one or more display pipes to render one or more display planes, each of the one or more display pipes comprising a set of graphics processing hardware resources for executing graphics commands and rendering graphics images in the one or more display planes; and pipe and plane management hardware logic to manage pipe and plane assignment, the pipe and plane management hardware logic to associate a first virtual machine (VM) with one or more virtual display planes and to maintain a mapping between the one or more virtual display planes and at least one physical display plane.

Apparatus and method for display virtualization using mapping between virtual and physical display planes

In various embodiments, an apparatus includes a system-on-chip (SoC) to be disposed in a vehicle having a plurality of cores; a hypervisor arranged to partition the cores into at least two domains, an operational domain and a failover domain; a first operating system (OS) arranged to manage execution of at least a first application in the operational domain to provide a first plurality of functions for the vehicle; a second OS arranged to manage execution of at least a second application in the failover domain to provide a second plurality of functions for the vehicle, on occurrence of a failure of the first application. The second functions comprise a subset of the first functions or less embellished versions of some of the first functions, and the second OS has less capabilities than the first OS. Other embodiments, including storage media and methods, are also described and claimed.

Failover support within a SoC via standby domain

A mechanism is described for facilitating localized load-balancing for processors in computing devices. A method of embodiments, as described herein, includes facilitating hosting, at a processor of a computing device, a local load-balancing mechanism. The method may further include monitoring balancing of loads at the processor and serving as a local scheduler to maintain de-centralized load-balancing at the processor and between the processor and other one or more processors.

De-centralized load-balancing at processors

An apparatus to facilitate partitioning of a graphics device is disclosed. The apparatus includes a plurality of engines and logic to partition the plurality of engines to facilitate independent access to each engine within the plurality of engines.

Graphics engine partitioning mechanism

Embodiments described herein provide techniques enable a compute unit to continue processing operations when all dispatched threads are blocked. One embodiment provides for a method comprising executing multiple concurrent threads on a processing resource of a graphics processor, during execution, detecting that each of the multiple concurrent threads of the processing resource are blocked from execution, selecting a victim thread from the multiple concurrent threads, and suspending the victim thread. The thread state is stored to a thread scratch space in memory along with a blocking event associated with the victim thread.

An apparatus to facilitate data prefetching is disclosed. The apparatus includes a memory, one or more execution units (EUs) to execute a plurality of processing threads and prefetch logic to prefetch pages of data from the memory to assist in the execution of the plurality of processing threads.

Thread prefetch mechanism

Embodiments described herein provide techniques enable a compute unit to continue processing operations when all dispatched threads are blocked. One embodiment provides for a graphics processor comprising a compute unit to execute multiple concurrent threads and a memory coupled with and on a same package as the compute unit. The memory can store thread state for a suspended thread and the compute unit can detect that multiple concurrent threads of the compute unit are blocked from execution. Upon detection, the compute unit can select a victim thread from the multiple concurrent threads, suspend the victim thread, store thread state of the victim thread to the memory, and select an additional thread to be executed. The compute unit can then replace the victim thread with an additional thread to be executed. The additional thread to be executed can be based on a blocking event for the additional thread.

Growing community of inventors

Portland, OR, United States of America

David J Cowperthwaite