U.S. Philips Corporation

David J Coe

David H Paxman

John A Slatter

Kenneth R Whight

John M Shannon

Franciscus A Schoofs

Royce Lowis

Philip H Bird

Carole A Fisher

Aart G Korteling

Richard J Tree

A photosensitive device includes a semiconductor body (1) having a first region (2) of one conductivity type adjacent a given surface (3) of the body with a second region (4) of the opposite conductivity type surrounding the first region (2) so as to form with the first region a main pn junction (5) terminating at the given surface (3), the main pn junction (5) being reverse-biassed in operation of the device. One or more further regions (6) of the one conductivity type surround the main pn junction (5) adjacent the given surface (3) so that each further region (6) forms a photosensitive pn junction (17) with the second region (4), the further region(s) (6) lying within the spread of the depletion region of the main pn junction (5) when the main pn junction (5) is reverse-biassed in operation of the device so as to increase the breakdown voltage of the main pn junction (5). Means are provided for transmitting light into the semiconductor body via the given surface to enable photogeneration of charge carriers in the vicinity of the photosensitive pn junction(s) (17). The further region(s) may include one or more annular floating regions (6') spaced apart from the main pn junction(s) and each other.

Photosensitive device suitable for high voltage operation

A semiconductor device and a circuit suitable for use in an intelligent power switch include an insulated gate field effect transistor (IGFET) (T2) and a power semiconductor switch (T1). The insulated gate field transistor IGFET (T2) is provided by a semiconductor body (6) which has a first region (7) of one conductivity type adjacent a given surface (6a) of the semiconductor body with the first region (7) forming at least part of a conductive path to a first main electrode of the power semiconductor switch. A second region (8) of the opposite conductivity type is provided within the first region adjacent the given surface (6a) and a third region (11) of the one conductivity type is provided adjacent the given surface (6a) within the second region (8), an area of the second region (8) underlying an insulated gate (14) provided on the given surface (6a) for defining a conduction channel (15) providing a gateable connection between the third region (11) and a fourth region (12) of the one conductivity type. The third and fourth regions (11 and 12) forming the source and drain regions of the IGFET and the second and third regions (8 and 11) together provide a zener diode, a conductive path being provided to the second region remote from the area underlying the insulated gate for reverse-biassing the zener diode. The IGFET may include a synchronous rectifier of a charge pump for providing a gate voltage signal to the power semiconductor switch which may be a power MOSFET (T2).

Semiconductor device and a circuit suitable for use in an intelligent

Low voltage semiconductor devices are integrated monolithically with a high voltage semiconductor device on an electrically conductive substrate. The substrate forms an electrode of the high voltage device and is connected in use to the high voltage terminal of a power supply. The low voltage devices operate from a regulated low voltage supply, which is regulated with reference to the high voltage supply voltage, and not with reference to ground. This reduces the need to isolate the low voltage devices from the conductive substrate. An intelligent power switch circuit constructed in accordance with the invention is suitable for use in automotive and lighting applications.

High voltage semiconductor with integrated low voltage circuitry

A method of manufacturing a semiconductor device in which a conductive layer (6) provided on a surface (4) of a semiconductor body (1) is formed with at least one opening (10). The semiconductor device may be an insulated gate field effect transistor (IGFET) in which case the opening (10) defines a hollow gate structure for the IGFET. Insulating material (16') is grown on the surface (4) to cover the conductive layer. The opening or openings (10) are sufficiently small and the growth of insulating material is continued for a sufficiently long period that insulating material growing on edges (8'a) of the conductive layer bounding the openings (10) meets to close the openings so that subsequent etching of the insulating material anisotropically towards the surface (4) to expose a surface of the conductive layer and/or to form a window (18) within insulating material covering an area of the semiconductor body surface larger than the openings and not covered by the conductive layer, leaves insulating material (19,17) on edges of the conductive layer so that the openings remain closed. Where the semiconductor device is an IGFET impurities to form the source and channel regions may be introduced via the window.

Method of manufacturing a DMOS device

A method of manufacturing a semiconductor device such as a lateral insulated gate field effect transistor is described in which impurities for forming first and second relatively shallow RESURF regions (8 and 11) of the opposite and the one conductivity type, respectively, are then introduced into the first region (4) and the semiconductor body is then heated first in an oxidizing atmosphere to cause the impurities to diffuse to form the RESURF regions (8 and 11) and to grow a relatively thick layer of insulating material on the given surface (3) at the same time. The relatively thick layer of insulating material is then defined to provide field oxide (14a) and gate oxide (14) then grown onto which is deposited a conductive gate layer (15,16) to form an insulated gate structure. Impurities are then introduced into the semiconductor body (3) using the insulated gate structure as a mask so as to form a lateral insulated gate field effect transistor (1).

Method of manufacturing lateral IGFETS including reduced surface field

A semiconductor device includes a bipolar transistor having an emitter region of one conductivity type formed in a base region of the opposite conductivity type, the base region being provided in a collector region of the one conductivity type. A first insulated gate field effect transistor provides a gateable connection to the emitter region of the bipolar transistor while a second insulated gate field effect transistor provides a charge extraction path from the base region when the bipolar transistor is turned off. The first insulated gate field effect transistor includes a further region of the other conductivity type provided in the emitter region, and a source region of the one conductivity type formed in the further region and an insulated gate overlying a channel area comprising at least part of the further region to provide a gateable connection between the emitter region and the source region of the first insulated gate field effect transistor. The second insulated gate field effect transistor having an insulated gate overlying a channel area comprising at least part of the emitter region adjacent the base region to provide a gateable connection between the base region and a source of the second insulated gate field effect transistor.

Semiconductor devices

A high voltage semiconductor device includes a two-dimensional array of polygonal regions in a higher resistivity body portion of the opposite conductivity type. The p-n junction between these regions and the body portion may be, for example, a drain junction of a D-MOS transistor or a collector junction of a bipolar transistor and is reverse-biased in at least a high voltage mode of operation. In order to relieve the high electric field at the corners of the polygonal regions, a plurality of further regions is distributed in each area of the body portion between facing corners of three or more of the polygonal regions. These further regions of the same conductivity type as the polygonal regions are located on at least one line from each of these corners in a symmetrical arrangement of the further regions within each area.

High voltage semiconductor devices

At least one annular region (11,12, . . . ) extends around an active device region (10) and is located within the spread of a depletion layer (25) from a reverse-biased p-n junction (20) formed by the device region (10) to increase the breakdown voltage of the junction (20). The device region (10) and/or at least one inner annular region (11,12, . . . ) includes at least one shallower portion (10b,11b, . . . ) which extends laterally outwards from a deep portion (10a,11a,12a, . . . ) and faces the surrounding annular region to change the spacing and depth relationship of these regions. This permits high punch-through voltages to be achieved between the regions (10,11,12, . . . ) while reducing peak fields at the bottom outer corners of the regions (10,11,12, . . . ). Inwardly-extending shallow portions (11c,12c, . . . ) may also be included. The shallow portions (10b,11b,11c,12c . . . ) may extend around the whole of a perimeter of the region or be localized where higher electrostatic fields may occur around the perimeter.

High voltage guard ring with variable width shallow portion

A field effect transistor, a bipolar transistor, a PIN diode, a Schottky rectifier or other high voltage semiconductor device comprise a semiconductor body having a depletion layer formed throughout a portion in at least a high voltage mode of operation of the device, such as, by reverse biasing a rectifying junction. The known use of a single high-resistivity body portion of one conductivity type to carry both the high voltage and to conduct current results in a series resistivity increasing approximately in proportion with the square of the breakdown voltage. This square-law relationship is avoided by the present invention in which a depleted body portion comprising an interleaved structure of first and second regions of alternating conductivity types carries the high voltage which occurs across the depleted body portion. The thickness and doping concentration of each of these first and second regions are such that when depleted the space charge per unit area formed in each of these regions is balanced at least to the extent that an electric field resulting from any imbalance is less than the critical field strength at which avalanche breakdown would occur in the body portion. The first regions in at least one mode of operation of the device provide electrically parallel current paths extending through the body portion.

High voltage semiconductor device

A semiconductor device having the advantages of bipolar transistor characteristics (such as a low ON resistance) and of FET characteristics (such as a rapid turn-off) can be obtained by integrating and merging together in one semiconductor body a bipolar transistor T and two or more insulated-gate FETs T1 to T4. A lateral FET T1 is formed by providing a drain region adjacent to the base region of the bipolar T and an insulated gate overlying an intermediate channel area. A further FET T3 which is of complementary conductivity type to T1 may have a source region provided in the drain region and an insulated gate over a channel area between the source region and the emitter region of T. These insulated gates are connected together, for example as a common gate grid, so permitting T1 to be turned on to extract charge from the base region of the bipolar T during turn off when T3 is turned off to interrupt the terminal connection to the emitter region of bipolar T. A vertical insulated-gate field-effect transistor T4 having the same source region as T3 may be formed in parallel with the bipolar transistor T to share the main current path through the device. A very compact power device structure can be obtained with a two-dimensional array of alternating base regions and drain regions.

Merged bipolar/field-effect transistors

Separate areas of an active unipolar barrier, e.g. a Schottky barrier, of a semiconductor device are located between closely-spaced field-relief regions which provide the device with an improved voltage blocking characteristic. The flow of minority carriers into the adjacent body portion under forward bias is restricted by providing, at least at the areas of the field-relief regions, a layer of different material from that of the body portion and from that of the unipolar barrier-forming means. The layer of different material may form a high-impedance electrical connection with the field-relief regions, and/or it may form with the body portion a heterojunction such as, for example, a Schottky barrier of higher barrier height, a barrier between different band gap materials or a MIS structure, which heterojunction forms part of the field-relief regions.

Semiconductor devices having field-relief regions

An insulated-gate field-effect transistor which may be of a vertical power D-MOS type includes surface-adjacent source and emitter regions surrounded in a semiconductor body by a surface-adjacent second region of opposite conductivity type. A third region adjoins the second region and has a lower conductivity-type determining doping concentration. At least a part of these second and third regions is located in a main current path from the source region to a drain of the transistor, and an insulated gate, which may be of metal-silicide, capacitively controls a conductive channel at least in this part of the second region. The emitter region is located at a side of the source region remote from the channel part and is separated therefrom by an intermediate part of the second region. The source region is electrically connected to this intermediate part, for example by a short-circuiting metal-silicide layer. A resistive current path in the second region is present below the emitter region and extends from this intermediate part to a further part of the second region which is electrically connected to the emitter region, for example by a short-circuiting metal-silicide layer. A source electrode is electrically connected to this further part so as to be electrically connected via the resistive current path to the source region. The emitter region serves to modulate the conductivity of the third region and thus reduce the drain series resistance of the transistor, by charge-carrier injection from the intermediate part when the source-drain current along the resistive current path is sufficient to forward-bias the intermediate part with respect to the third region.

Insulated-gate field-effect transistors

An insulated-gate field-effect transistor which may be of the D-MOS or V-MOS type includes a source region (1) which is surrounded by a second region (2) of opposite conductivity type, itself surrounded by a third region (3) associated with the transistor drain (4). An insulated gate (12) of the transistor is present on a channel area of the second region (2) between the source region (1) and a first part (31) of the third region (3). The third region (3) also has a surface-adjoining second part (32) which is remote from the first part (31) and preferably has a lower doping concentration than the second and source regions (2, 1). An electrode layer (11) which may be the source electrode extends on said second part (32) of the third region (3) and is connected to said second region (2), and there is present between this electrode layer (11) and the second part (32) of the third region (3) a Schottky junction (33) having a lower forward voltage drop than the p-n junction (34) between the second and third regions (2,3). The transistor can have a fast switching speed even when driving inductive loads, since the Schottky junction (33) suppresses minority carrier injection at the forward-biased p-n junction (34) during voltage overswings. Preferably the second part (32) of the third region (3) is laterally bounded by the second region (2) which forms a guard ring for the Schottky junction (33) so maintaining a high blocking voltage capability. In order to further suppress minority carrier injection the electrode layer (11) preferably forms with the second region (2) a Schottky junction around which the source region (1) preferably extends as a guard ring.

A vertical insulated gate field effect transistor is made by providing a polycrystalline semiconductor layer on an insulating layer at a surface of an n-type semiconductor body, and thereafter forming gates of the IGFET by laterally diffusing a p-type impurity into the polycrystalline semiconductor layer below two opposite edges of a masking layer. A p-type zone and an n-type source zone are then formed at the surface of the semiconductor body by introducing the relevant impurities in the presence of the masking layer, and then by laterally diffusing these impurities below the gate with the p-type impurities for the p-type zone diffusing laterally farther beneath the gate than the n-type impurities of the source zone. The lateral extent of the source zone, the p-type zone, and the gates can all be predetermined in relation to the same edge of the masking layer which enables improved gate-channel alignment, and so minimizes Miller capacitance of the IGFET.

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East Grinstead, United Kingdom

David J Coe