Ncr Corporation

Peerless Systems Corporation

Teradata Us, Inc.

Teradata Corporation

David J Chura

Robert J McMillen

M Cameron Watson

Stephen Laurence Schafer

Philip M Neches

A multistage interconnect network (MIN) capable of supporting massive parallel processing, including point-to-point and multicast communications between processor modules (PMs) which are connected to the input and output ports of the network. The network is built using interconnected switch nodes arranged in 2 [logN] stages, wherein b is the number of switch node input/output ports, N is the number of network input/output ports and [logN] indicates a ceiling function providing the smallest integer not less than logN. The additional stages provide additional paths between network input ports and network output ports, thereby enhancing fault tolerance and lessening contention.

Reconfigurable, fault tolerant, multistage interconnect network and protocol

A multistage interconnect network (MIN) capable of supporting massive parallel processing, including point-to-point and multicast communications between processor modules (PMs) which are connected to the input and output ports of the network. The network is built using interconnected switch nodes arranged in 2 &#x250c;logN&#x2510; stages, wherein b is the number of switch node input/output ports, N is the number of network input/output ports and &#x250c;logN&#x2510; indicates a ceiling function providing the smallest integer not less than logN. The additional stages provide additional paths between network input ports and network output ports, thereby enhancing fault tolerance and lessening contention.

Multistage interconnect network combines back channel replies received from destinations into a single result and transmits to the source

A method and apparatus for the compression of complex bi-level images created from gray scale images. The invention has particular application when used with continuous raster scan output devices such as laser printers where the invention enables the printing of images using a smaller amount of memory than would be needed without the invention. To practice the invention, a bi-level gray scale image is produced by any desired technique. The gray scale image is then rendered thereby converting it to a bi-level image. The bi-level image is compressed in portions The compressed portions are then decompressed and the decompressed portions are sent to a print engine of a continuous raster scan device at the speed required by the print engine so that it is never necessary to have the entire image stored in the printer's memory at the same time.

Bi-level image compression by gray scale encoding

A multistage interconnect network (MIN) capable of supporting massive parallel processing, including point-to-point and multicast communications between processor modules (PMs) which are connected to the input and output ports of the network. The network is built using interconnected switch nodes arranged in 2 &verbar;log,N&verbar; stages, wherein b is the number of switch node input/output ports, N is the number of network input/output ports and &verbar;log,N&verbar; indicates a ceiling function providing the smallest integer not less than log,N. The additional stages provide additional paths between network input ports and network output ports, thereby enhancing fault tolerance and lessening contention.

Multistage interconnect network uses a master processor to perform dynamic configuration for all switch nodes based on a predetermined topology

A multistage interconnect network (MIN) capable of supporting massive parallel processing, including point-to-point and multicast communications between processor modules (PMs) which are connected to the input and output ports of the network. The network is built using interconnected switch nodes arranged in 2 .left brkt-top. log.sub.b N .right brkt-top. stages, wherein b is the number of switch node input/output ports, N is the number of network input/output ports and .left brkt-top. log.sub.b N .right brkt-top. indicates a ceiling function providing the smallest integer not less than log.sub.b N. The additional stages provide additional paths between network input ports and network output ports, thereby enhancing fault tolerance and lessening contention.

Computer system using a master processor to automatically reconfigure

A method and system which enables the printing of all pages that an interpreter of a page description language can image at the highest print quality that can be maintained while ensuring that all pages will print regardless of complexity. A memory manager is responsible for allocation of memory for rendering pages and a fallback manager is responsible for handling memory overflow and video underrun exceptions.

Fallback processing for page generation using memory reduction techniques

A multistage interconnect network (MIN) capable of supporting massive parallel processing, including point-to-point and multicast communications between processor modules (PMs) which are connected to the input and output ports of the network. The network is built using interconnected switch nodes arranged in 2 log.sub.b N stages, wherein b is the number of switch node input/output ports, N is the number of network input/output ports and log.sub.b N indicates a ceiling function providing the smallest integer not less than log.sub.b N. The additional stages provide additional paths between network input ports and network output ports, thereby enhancing fault tolerance and lessening contention.

Growing community of inventors

Redondo Beach, CA, United States of America

David J Chura