Rambus Inc.

Semtech Corporation

Semtech Canada Corporation

Snowbush Inc.

Rambus Canada Inc.

David J Cassan

Marcus Van Ierssel

Mehrdad Ramezani

Christopher D Holdenried

Saman Sadr

Sang-Wook Paul Park

Chris Holdenried

Mohamed Abdalla

Afshin Rezayee

Kamran Farzan

Kenneth William Martin

Angus William McLaren

A clock and data recovery circuit (CDR) includes a digitally controlled oscillator (DCO). A data sampler is coupled to receive a clock signal from the DCO. A deserializer includes an input coupled to an output of the data sampler. A first phase detector is coupled between a first output of the deserializer and a first input of the DCO. A second phase detector is coupled to a second output of the deserializer. An accumulator is coupled between an output of the second phase detector and a second input of the DCO. A frequency lock detection block is coupled to an output of the accumulator. An eye monitor is coupled to an input of the data sampler. The first phase detector controls a delay of the DCO and the accumulator controls a frequency of the DCO. An edge mute signal is coupled to the deserializer.

Deserialized dual-loop clock radio and data recovery circuit

A decision feedback equalizer, transceiver, and method are provided, the equalizer having at least one comparator, the at least one comparator comprising a first stage, comprising a main branch having two track switches with a resistive load, an offset cancellation branch, a plurality of tap branches with transistor sizes smaller than the main branch, in which previous decisions of the equalizer are mixed with the tap weights using current-mode switching, and a cross coupled latch branch; and a second stage, comprising a comparator module for making decisions based on the outputs of the first stage and a clock input, and a plurality of flip-flops for storing the output of the comparator module.

Decision feedback equalizer and transceiver

A high speed transmit driver is provided, along with methods to improve driver slew rate, decrease transmit jitter, improve termination accuracy, and decrease sensitivity to supply noise.

High-speed SSR transmit driver

A fractional-N frequency synthesizer is described that includes a voltage controlled oscillator (VCO), a programmable integer divider, and a glitch-free phase rotator. The phase select inputs of the phase rotator are controlled by a delta-sigma modulator to provide fine frequency resolution in addition to randomization and noise shaping of fractional quantization noise. The delta-sigma modulator is clocked at rates higher than the synthesizer reference clock resulting in an improvement in clock jitter at the output of the frequency synthesizer. A glitch-free phase multiplexer design is used to implement the phase rotator fractional divider to enables operation at rates higher than the reference clock. The over-sampling ratio of the delta-sigma modulator over the reference clock frequency of the PLL translates directly into an improvement in the quality of the output clock with respect to fractional quantization noise, phase mismatch, and digital noise injection.

System and method for jitter control

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Toronto, Canada

David J Cassan