Sun Microsystems, Inc.

3par Inc.

3pardata, Inc.

David J Broniarczyk

Ashok Singhal

George R Cameron

Bjorn O Liencres

Erik E Hagersten

Nalini Agarwal

Jeffrey A Price

Frederick M Cerauskis

Jeff Price

Gerald Cheung

Jeff A Price

Brian L Smith

James Ray Lewis

George C Cameron

A communication link protocol is provided for communicating between nodes of an interconnect system via a communication link. In one embodiment, the communication link protocol includes a direct memory access (DMA) command for writing a block of data from a local node to a remote node via the communication link; an administrative write command for writing data from a local node to registers in a remote node via the communication link for administrative purposes; a memory copy write command for writing a line of memory from a local node to a remote node via the communication link when any data is written into that line of memory; and a built in self test (BIST) command for testing the functionality of the communication link.

Communication link protocol optimized for storage architectures

A method is provided for communicating data in an interconnect system comprising a plurality of nodes. In one aspect, the method includes: issuing a command packet from a first node, the command packet comprising a respective header quadword and at least one respective data quadword for conveying a command to a second node, wherein the command is selected from a group comprising a direct memory access (DMA) command, an administrative write command, a memory copy write command, and a built in self test (BIST) command; receiving the command packet at the second node; issuing an acknowledgement packet from the second node, the acknowledgement packet comprising a respective header quadword for conveying an acknowledgement that the command packet has been received at the second node.

Method of communicating data in an interconnect system

A node controller for a data storage system having at least one node provides access to a data storage facility. The node controller is distinct from a computer-memory complex of the node. The node controller provides overall control for transferring data through the node.

Node controller for a data storage system

A data storage system includes a plurality of nodes for providing access to a data storage facility. Each node has a computer-memory complex to provide general purpose computing for the node, a node controller to control data transfers through the respective node, and a cluster memory to buffer data for the data transfers. A plurality of communication paths interconnect the nodes, with a separate communication path provided for each two nodes of the data storage system.

Data storage system

A system and method for testing signal interconnections using built-in self test (BIST). BIST functionality is designed into the various chips of a computer system. These chips include a transmit unit, a receive unit, a control logic unit, and a central logic unit. A control logic unit associated with a signal block (i.e. a group of signals) configures the signal block for either testing or normal operation. The central logic unit performs test pattern generation for all signal blocks on a given chip. Chips may act as either a master or slave chip during testing. When acting as a master chip, the transmit unit of the chip drives test patterns onto one or more signal lines. The receive unit of the slave chip returns a corresponding test pattern to the master chip after receiving the transmitted test pattern. A receive unit on the master chip receives the corresponding test patterns and performs verification. All tests occur at the operational clock speed of the computer system. A master and a slave chip need not be mounted upon the same circuit board, allowing for tests through connectors within a computer system.

System and method for testing signal interconnections using built-in self test

Snooping is implemented on a split transaction snooping bus for a computer system having one or many such buses. Circuit boards including CPU or other devices and/or distributed memory, data input/output buffers, queues including request tag queues, coherent input queues ('CIQ'), and address controller implementing address bus arbitration plug-into one or more split transaction snooping bus systems. All devices snoop on the address bus to learn whether an identified line is owned or shared, and an appropriate owned/shared signal is issued. Receipt of an ignore signal blocks CIQ loading of a transaction until the transaction is reloaded and ignore is deasserted. Ownership of a requested memory line transfers immediately at time of request. Asserted requests are queued such that state transactions on the address bus occur atomically logically without dependence upon the request. Subsequent requests for the same data are tagged to become the responsibility of the owner-requestor. A subsequent requestor's activities are not halted awaiting grant and completion of an earlier request transaction. Processor-level cache changes state upon receipt of transaction data. A single multiplexed arbitration bus carries address bus and data bus request transactions, which transactions are each two-cycles in length.

Implementing snooping on a split-transaction computer system bus

A split transaction snooping bus protocol and architecture is provided for use in a system having one or many such buses. Circuit boards including CPU or other devices and/or distributed memory, data input/output buffers, queues including request tag queues, coherent input queues ('CIQ'), and address controller implementing address bus arbitration plug-into one or more split transaction snooping bus systems. All devices snoop on the address bus to learn whether an identified line is owned or shared, and an appropriate owned/shared signal is issued. Receipt of an ignore signal blocks CIQ loading of a transaction until the transaction is reloaded and ignore is deasserted. Ownership of a requested memory line transfers immediately at time of request. Asserted requests are queued such that state transactions on the address bus occur atomically logically without dependence upon the request. Subsequent requests for the same data are tagged to become the responsibility of the owner-requestor. A subsequent requestor's activities are not halted awaiting grant and completion of an earlier request transaction. Processor-level cache changes state upon receipt of transaction data. A single multiplexed arbitration bus carries address bus and data bus request transactions, which transactions are each two-cycles in length.

Split transaction snooping bus protocol

In a multiprocessor system having a shared memory, each central processor services copyback requests from other central processors. Each central processor has a writeback buffer along with a plurality of tag buffers and an associated snoop architecture for processing writeback and copyback commands. Each central processor includes a cache subsystem having a system interface, a main cache and an associated tag array. The system interface has an address controller and data controller, each having separate input and output queues for interfacing between the central processor and system control and data buses. The address controller includes a set of duplicate tags that mirror the tags associated with the main cache, and an auxiliary tag input buffer and auxiliary tag output buffer. The address controller has for each line in the output queue an associated pointer that indicates the location in the data controller where data is stored that is associated with output queued commands. In operation, the address controller processes inbound multiple copyback requests without requiring the central processor to access data from its associated main cache. The address controller utilizes the output queues in the address and data controller as well as the auxiliary tag buffers to store copyback data and tag information.

Growing community of inventors

Mountain View, CA, United States of America

David J Broniarczyk