International Business Machines Corporation

David J Bradley

Richard Edwin Harper

Steven Wade Hunter

Donald J Kostuch

Richard Alan Dayan

Michael Robert Turner

Bruce Alan Smith

Alan Richard Tannenbaum

Lewis C Eggebrecht

William Brooks Ott

Martin A Reed

Dennis D Gibbs

Bradly J Konopik

James S Martin

Dennis S Gibbs

Linda K Buckley

Robert E Berens

A method for managing power consumption of multiple computer servers is disclosed. The number of computer servers required to meet a current workload demand is initially determined. Next, a thermally optimized configuration of powered-on computer servers to meet the current workload demand is determined. At least one computer server is powered on or powered off, based on the thermally optimized configuration.

Method for managing power consumption of multiple computer servers

A method for managing power consumption of multiple computer servers is disclosed. The current workload information and the current capacity information of a group of computer servers within a computer server pool are determined. A short term history and a long term history of the workload information are then built based on the determined workload information. Next, the information regarding short-term variations in workload is determined. Similarly, the information regarding long-term variations in workload is determined. Based on a combination of the above-mentioned determined short-term and long-term information, at least one of the computer servers is powered on or powered off.

Diskette media and drive determination in which a diskette controller attempts to read the diskette according to a variety of formats having, for instance, different data transfer rates. A successful read is registered by the controller and that format is thereafter identified with the diskette drive and the diskette media inserted in the drive.

Diskette drive and media type determination

A system is disclosed for managing a plurality of interrupt handlers in a linked-list data structure, for servicing a plurality of input/output devices sharing a common interrupt line in a microcomputer. The system provides for an orderly method to link a newly loaded interrupt handler routine into a linked-list data structure consisting of previously loaded interrupt handler routines. The system further provides for an orderly method to share a common interrupt line among a plurality of input/output devices being serviced by the interrupt handlers. The system further provides for an orderly means to unlink a particular interrupt handler routine from the linked-list data structure when a corresponding input/output device is to be deactivated. The system finds special utility in a multitasking operating system environment where input/output devices can be deactivated in a different sequence from that in which they were originally activated.

System for managing a plurality of shared interrupt handlers in a

An interrupt interface circuit for interrupt level sharing comprising a pulse generator having an open-collector or tri-state output connected to an external interrupt line shared by other similar circuits. An active internal interrupt signal causes the pulse generator to pulse. The external interrupt line is fed back and latched on a disabling input of the pulse generator so that any pulse on the external interrupt line prevents further pulsing. The software handler of the interrupt, upon servicing an interrupt of the interrupt level, causes the enabling of the pulse generators of that level, thereby permitting active internal interrupt signals to produce a further pulse. By this interrupt level sharing, phantom interrupts are eliminated and servicing overhead is minimized. R

Interrupt level sharing

In a computer system, paging operates and a method of use thereof are provided for extending the addressing capability of a processor by using a page register. The page register includes means for storing different codes for different operations to be performed on the memory. The memory is divided into four groups of memory within 2.sup.n addresses such that there is paged and unpaged ROM and pages and unpaged RAM. The unpaged ROM and RAM include only a single block which is directly addressed by the n bit address bus. The paged ROM and RAM includes a plurality of blocks or pages, one of which is selected to be addressed by the page register. The page register responds to the address bus and to signals from the processor defining the memory operation to be performed by providing page signals, selecting one page of paged memory. The method of using the paging apparatus includes creating a table in the unpaged RAM of all routines in the paged memory blocks and using the table to transfer from one routine to another. Within the table is a code identifying the page in which the new routine exists and an offset into that page used to determine the address in that page of the new routine.

Page addressing mechanism

An apparatus and method for scrolling windows of both graphic and graphic encoded text information on a raster scan display. The apparatus includes a processor which references a program store, and a video refresh buffer, the buffer containing graphic and graphic encoded text data in a pixel format adapted for directly refreshing the display. The processor is operated under control of the program store and responsive to information specifying the pixel locations of opposite corners of a window to be scrolled and the number of rows to be scrolled for calculating the size and location in the display refresh buffer of the window to be scrolled, and for moving the number of rows to be scrolled from source locations to destination locations within the window in the display refresh buffer.

Apparatus and method for scrolling text and graphic data in selected

Apparatus and method for writing text characters to a raster scan video display operated in an all-points-addressable, or graphics, mode, and for reading characters thus written. A graphic video display buffer directly refreshes the display with graphics data received from a microprogrammed processor. The processor writes a character to the display by selecting and loading into the graphics video display buffer a text character dot pattern retrieved from main storage, and reads a character previously written by comparing a dot pattern retrieved from the display buffer with dot patterns retrieved from main storage. To write a character to the display in color, the graphic dot image of a selected character retrieved from main storage is expanded to a selected pixel and color format, and stored in the graphics video display buffer. Text characters thus written in color are read by retrieving from the display buffer the expanded dot image, restoring the expanded dot image to its original form, and comparing the restored dot image with graphic dot images retrieved from storage.

Apparatus and method for reading and writing text characters in a

In a computer system, paging operates and a method of use thereof are provided for extending the addressing capability of a processor by using a page register. The page register includes means for storing different codes for different operations to be performed on the memory. The memory is divided into four groups of memory within 2.sup.n addresses such that there is paged and unpaged ROM and paged and unpaged RAM. The unpaged ROM and RAM include only a single block which is directly addressed by the n bit address bus. The paged ROM and RAM includes a plurality of blocks or pages, one of which is selected to be addressed by the page register. The page register responds to the address bus and to signals from the processor defining the memory operation to be performed by providing page signals, selecting one page of paged memory. The method of using the paging apparatus includes creating a table in the unpaged RAM of all routines in the paged memory blocks and using the table to transfer from one routine to another. Within the table is a code identifying the page in which the new routine exists and an offset into that page used to determine the address in that page of the new routine.

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Boca Raton, FL, United States of America

David J Bradley