Intel Corporation

David J Ayers

Vivek Tiwari

Edward Thomas Grochowski

Stefan Rusu

James Steven Burns

Ian A Young

David J Sager

Sandeep Ahuja

Robin A Steinbrecher

Susan F Smith

Dan R McCutchan

Marsha Eng

Harry Muljono

Sudarshan Kumar

Kenneth D Shoemaker

Srikanth Balasubramanian

Zhiguo Wang

William A Samaras

Yanmei Tian

Stephen M Ramey

Bill Samaras

Mubeen Atha

Sukirti Gupta

Tom E Wang

In an embodiment, a processor includes voltage calculation logic to calculate a plurality of maximum operating voltage values each associated with a number of active cores of the plurality of cores, based at least in part on a plurality of coefficient values. In this way, the processor can operate at different maximum operating voltages dependent on the number of active cores. Other embodiments are described and claimed.

Calculating a dynamically changeable maximum operating voltage value for a processor based on a different polynomial equation using a set of coefficient values and a number of current active cores

An apparatus may include an integrated circuit die having a plurality of temperature sensors and a control unit integrated thereon. The control unit can calculate an average die temperature based on readings from the plurality of temperature sensors, compare the average die temperature to a specification temperature and control an off-die cooling system based on the comparison.

Sensor-based thermal specification enabling a real-time metric for compliance

A system for delivering power to a device in a specified voltage range is disclosed. The system includes a power delivery network, characterized by a response function, to deliver power to the device. A current computation unit stores values representing a sequence of current amplitudes drawn by the device on successive clock cycles, and provides them to a current to voltage computation unit. The current to voltage computation unit filters the current amplitudes according to coefficients derived from the response function to provide an estimate of the voltage seen by the device. Operation of the device is adjusted if the estimated voltage falls outside the specified range.

Mechanism for estimating and controlling di/dt-induced power supply voltage variations

A method and apparatus for compensating for current-change induced voltage changes is disclosed. In one embodiment, a digital throttle unit coupled to an instruction pipeline may generate a compensating current signal, which may then cause a dummy load to consume a compensating current. In another embodiment, a counter responsive to changes in clock frequency may generate a ramp current signal, which may then cause a dummy load to consume a current corresponding to the ramp current signal.

Method and apparatus to limit current-change induced voltage changes in a microcircuit

With some transmitter embodiments disclosed herein, static power consumption in low power modes may be reduced without excessively increasing latency.

Link transmitter with reduced power consumption

A method for adjusting the voltage and frequency to minimize power dissipation in a processor. The method of one embodiment comprises determining a power consumption value. The power consumption value is evaluated to obtain a new operating point. The new operating point is compared with a present operating point. A frequency setting and a voltage setting are adjusted to correspond to the new operating point if the new operating point is different from the present operating point.

Method and apparatus for adjusting the voltage and frequency to minimize power dissipation in a multiprocessor system in response to compute load

A processor includes a digital throttle to monitor the activity of various units of the processor's instruction execution pipeline. The monitored activity is scaled according to the current operating point of the processor and a power state is determined from the scaled activity. If the power state reaches a first threshold, the operating point of the processor is adjusted and a new scaling factor is selected to determine the power state.

Digital throttle for multiple operating points

Method and apparatus for adjusting the voltage and frequency to minimize power dissipation in a multiprocessor system

A mechanism is disclosed for determining a voltage at a device in a power delivery network. The mechanism includes determining an impulse response for the power delivery network, and tracking the current consumed by the device as it operates over a sequence of clock cycles. The activity profile is filtered using a representation of the impulse response to provide a profile of the voltages at the device.

Simulation of di/dt-induced power supply voltage variation

A processor includes a digital throttle to monitor the activity of various units of the processor's instruction execution pipeline, and to determine a power state for the processor from the monitored activity. One of two or more power control mechanisms is engaged, responsive to the power state of the processor reaching a threshold.

Multiple mode power throttle mechanism

The present invention provides a mechanism for adjusting the activity of an integrated digital circuit such as a processor to reduce voltage changes attributable to current changes triggered by clock gating. The processor includes one or more functional units and a current control circuit that monitors activity states of the processor's functional units to estimate the current consumed over n clock cycles. The current control circuit estimates the current change for a given clock cycle from the n activity states and compares the estimated current change with first and second thresholds. The processors activity is decreased if the estimated current change is greater than the first threshold, and the processor activity is decreased if the estimated current change is less than the second threshold.

Mechanism to control di/dt for a microprocessor

An improved connector scheme for a power pod power delivery system provides a low-resistance, low inductance path between a power source and a power consuming module. Specifically, the present invention is a connector scheme comprising a printed circuit board having a plurality of sets of planar pads, each of the plurality of sets of planar pads being coupled to a power source and/or a signal source, and a flexible connection for detachably coupling with each of the plurality of sets of planar pads on the printed circuit board.

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Fremont, CA, United States of America

David J Ayers