Motorola Corporation

Alliedsignal Inc.

David J Anderson

Danny A Bersch

Howard C Anderson

Stephen Frederic Yates

Jerald A Hallmark

Daniel David Alexander

Romulus Gaita

Robert Henry Sedath

Doug Garrity

Brad D Gunter

Jian-Kun Shen

Michael Peter Straszewski

Douglas Alan Garrity

Cezary Antoni Marcjan

Daniel S Marshall

Tomasz L Klosowiak

Robert Michael Gardner

Roy E Hunninghaus

Gary L Christopher

Gary J Seminara

Christopher P Thron

Michael B Thomas

John T Meagher

Kenneth B Riordan

Ellen Lan

Kevin M Andrews

Joseph P Tomase

Gary Joseph Seminara

Neil R Peplinski

Irene C G DeFilippi

Irene C DeFilippi

A method for predistorting a digital signal prior to amplification is disclosed in which a look-up table is computed using power values of digital input signal samples as look-up values. The look-up table is preferably a function of pre-measured calibration data. The look-up table is applied to digital input signals for producing the predistorted signal. Computing the look-up table may include determining a set of input power values, obtaining the pre-measured calibration data including an output power data value and phase data value of the amplifier corresponding to each of the input power values, and deriving a set of calibration power values using the output power data values. The calibration power values and the input power values are then used to derive amplitude predistortion calibration values while the phase data values are used to determine phase predistortion calibration values. The calibration power values and corresponding amplitude predistortion calibration values are interpolated to provide amplitude predistortion values while the calibration power values and corresponding phase predistortion calibration values are interpolated to provide phase predistortion values. The look-up table is computed from the amplitude predistortion values and the phase predistortion values.

Digital predistortion for amplifiers

A flexible circuit board and a method for making a flexible circuit board. The flexible circuit board (,) is formed from a substantially rigid material and includes a first portion (,) and a second portion (,) coupled by a bend region (,). The bend region (,) includes at least one bend (,) having a radius less than 120 mils.

Flexible circuit board and method for making a flexible circuit board

A method is provided for configuring a programmable semiconductor device. The method includes using the configuration data of a macro (,A) or a plurality of macros to configure the programmable semiconductor device. The configuration data of the macro (,A) is combined with the configuration data of a work area (,). The programmable semiconductor device is configured using the combined configuration data of the macro (,A) and the work area (,).

Method for configuring a programmable semiconductor device

A titania bound ion exchange composition is prepared by admixing crystalline sodium titanate and a hydrolyzable titanium compound and then drying the titania bound crystalline sodium titanate. The dried titania bound ion exchange composition is subjected to optional compaction and calcination steps to improve the physical strength of the titania bound composition.

Titania bound sodium titanate ion exchanger

A receiver (,) corrects for dynamic DC offsets by utilizing an open loop predictive DC offset correction stage (,) to respond instantly to changes in AGC settings on a timeslot by timeslot basis. The receiver has an AC coupled baseband receiver and has memory (,) for storing calibration offset data (,and,) representing a calibration offset voltage value for each automatic gain control (AGC) state determined relative to a known reference value. The predictive DC offset stage (,) predicts a predictive DC offset correction value (,and,) for a selected timeslot using stored calibration offset data (,and,) and an average of stored calibration offset data corresponding to AGC states for all timeslots in a given frame.

Cellular TDMA base station receiver with dynamic DC offset correction

A process for fabricating an electronic module (,) and a packaged electronic device (,) having a thermally conductive substrate includes the step of thermally spraying of a dielectric layer (,) onto a baseplate (,). An electrically conductive layer (,) is then direct bonded to the thermally sprayed dielectric layer. The thermally sprayed dielectric layer can be formed at selected locations on the upper surface of the baseplate (,) by forming a pattern on the upper surface prior to carrying out the thermal spraying process. The electrically conductive layer (,) is patterned to form an interconnect pattern overlying the baseplate. Because the thermal spraying process can form extremely thin dielectric layers, an electronic module (,) fabricated in accordance with the invention exhibits high heat transfer characteristics. A heat producing electronic component (,), such as a power transistor, can be attached to the electrically conductive layer (,), and the heat generated therefrom dissipated through the baseplate (,).

Process for fabricating electronic devices having a thermally conductive substrate

A system for laying out a capacitor array (400) implements a programmable capacitor (33-39) whose operation is controlled with a binary control word. A programmable capacitance is produced by coupling binary weighted, switchable capacitors (101-107) between terminals (51, 52) of the programmable capacitor. The capacitor array includes two or more unit capacitors (101, 103) of unequal areas. The other capacitors in the array are derived by interconnecting multiple capacitors that match one of the unit capacitors. Die area is reduced while accuracy is maintained by controlling the larger unit capacitor with the least significant bit of the binary control word whenever possible and using the smaller unit capacitor only as a trim capacitor.

Programmable analog array and method

A circuit and method control the common-mode potential at an output (17, 18) of a fully differential amplifier (32) by feeding forward a common-mode correction signal through the amplifier. An input signal (V.sub.IN+ -V.sub.IN-) is amplified in the amplifier to produce a differential output signal (V.sub.O- -V.sub.O+) at the output. A common potential of the differential inputs (37, 38) of the amplifier is sensed with a transistor (54, 56) biased to a reference voltage (V.sub.CM) and amplified through the amplifier to produce a common-mode correction signal to offset a common-mode component of the differential output signal. A feedback circuit (33-36) is used to develop the common potential from the common-mode component.

Amplifier with input referred common-mode adjustment

A comparator (12) and method compare first and second signals (V.sub.IN+, V.sub.IN-) to provide an output signal (V.sub.O, V.sub.OB). A transistor (43) couples a supply terminal (64, 66) of the comparator to a power supply (V.sub.DD) to enable the comparator for comparing the first and second signals. When the output signal is valid, it turns off the transistor to isolates the supply terminal from the power supply. As a result, power is reduced and a change in the first and second signals is prevented from changing the output signal. When the transistor turns off, a charge is trapped on the supply terminal that unbalances the comparator and causes a comparison error. A balanced condition is restored with a discharge circuit (31-33) coupled to the supply terminal to alter the charge when a control signal (RESET) is applied.

Analog comparator and method

This invention is method for preparing a titania bound ion exchange composition comprising admixing crystalline sodium titanate and a hydrolyzable titanium compound and, thereafter drying the titania bound crystalline sodium titanate and subjecting the dried titania bound ion exchange composition to optional compaction and calcination steps to improve the physical strength of the titania bound composition.

A variable conducting element (10) and method for programming a constant current or constant resistance provided at output terminals (24 and 26) of a ferroelectric transistor (12). The ferroelectric transistor (12) has portions of a ferroelectric material (32A) programmed having up-polarization states separated by domain walls (34) from portions of a ferroelectric material (32B) programmed having down-polarization states. The portion of the ferroelectric material (32A) programmed in the up-polarization state forms current conduction channels between a source region (23) and a drain region (25) of the ferroelectric transistor (12). The ferroelectric transistor (12) is programmed through a capacitor (14) to adjust the charge supplied to a control terminal (22) of the ferroelectric transistor (12).

Variable conducting element and method of programming

A ferroelectric transistor (72) is programmed with a gate voltage that shifts a threshold voltage of the ferroelectric transistor (72). The shifted threshold voltage generates a correction current (.DELTA.I.sub.(N-1)) in a combination circuit (52) that trims an output voltage of a DAC trim circuit (50). A ferroelectric material (32) of the ferroelectric transistor (72) stores a charge in accordance with a programming voltage and allows a dynamic adjustment of the correction current (.DELTA.I.sub.(N-1)) that is used to modify the output voltage of the DAC trim circuit (50).

Digital-to-analog converter and method of calibrating

An electronic control module (10) includes a circuit substrate (12) containing a plurality of thermal vias (36) and a heat-generating electronic device (26) attached to the thermal vias (36). The circuit substrate (12) is attached to a mounting plate (18) by a plurality of electrically-isolated, thermal attachment pads (20) located at selected positions on an electrically insulating layer (16) overlying a metal baseplate (14). A solder layer (22) functions to both mechanically attach the plurality of thermal vias (36) to the plurality of thermal attachment pads (20), and to provide a thermal dissipation pathway for heat generated by the electronic devices (26). The heat is transferred from the circuit substrate (12) through the plurality of thermal attachment pads (20) to the metal baseplate (14).

Solder bonded electronic module

A programmable analog array (10) comprises an array of configurable cells (11), each cell (11) including analog circuitry (12) and digital circuitry (14). The cells (11) are configured for a particular functional application. The digital circuitry (14) converts an analog signal generated by the analog circuitry (12) into digital control information, which is then used to adjust the analog circuitry (12). Therefore, the analog circuitry (12) and the digital circuitry (14) form a digital feedback loop. The digital feedback loop is established either within a single cell or among neighboring cells. Thus, the digital feedback loop is established without using a global data bus.

Programmable analog array and method for establishing a feedback loop

A programmable analog array (10) comprises an array (11) of cells, each cell including analog circuitry (12), a switch control circuit (18), and a digital storage element (16). The switch control circuit (18) receives a clock signal and sequentially configures the circuits within the analog circuitry (12) to realize different circuit functions in accordance with configuration data stored in different digital memory units (17A-17D) within digital storage element (16). During a time interval, the analog signals generated by the analog circuitry (12) before that time interval are stored in an analog storage element (14), which is constructed from a portion of a capacitor network (54) in the analog circuitry (12) and is partitioned into a set of analog memory units (56A-56D). Each analog memory unit (56A-56D) stores the analog signal for a corresponding phase of the clock signal.

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Scottsdale, AZ, United States of America

David J Anderson