Xilinx, Inc.

David I Lawrie

David Andrews

Colin Stirling

Elizabeth R Cowie

Jeffrey Allan Graham

William A Wilkie

Graham Johnston

Approaches are disclosed for encoding N symbols of a sequence in parallel using an R parity symbol encoding algorithm. A first symbol matrix is added to a first parity matrix over a finite field to produce a first intermediate matrix. The first intermediate matrix is multiplied by at least a first coefficient matrix and a second coefficient matrix over the finite field to produce a second intermediate matrix. A second symbol matrix is multiplied by at least the second coefficient matrix to produce a third intermediate matrix. The second and third intermediate matrices are added to produce a revised parity matrix.

Circuit for forward error correction encoding of data blocks

In one embodiment, a method of block decoding is provided. For each of a plurality of data blocks input to a memory arrangement, a plurality of decoding iterations are performed using a circular pipeline of processing stages. For each decoding iteration, one processing stage of the circular pipeline performs a first set and a second set of soft-input-soft-output (SISO) decoding operations on a block of data. The first set of SISO decoding operations produces an intermediate block of data. The second set of SISO decoding operations is performed on the intermediate data block to complete the one decoding iteration. The next decoding iteration of the plurality of decoding iterations is performed using the next processing stage following the one processing stage of the circular pipeline of processing stages.

Pipelined turbo convolution code decoder

In one embodiment, a circular pipeline processing system is provided. The system includes a plurality of processing stages configured to operate in a circular pipeline. Each processing stage is configured to output a fully processed data block in response to completing a final processing iteration, and otherwise, store a partially processed data block in a memory buffer of the processing stage. Each processing stage is configured to select between an unprocessed data block and a partially processed data block from the memory buffer of a preceding processing stage, based on one or more of availability of memory sufficient for storage of an unprocessed data block or availability of a partially processed data block. The processing stage is configured to process the selected data block.

Circular pipeline processing system

A method for decoding an encoded message is described. The method includes obtaining a set of metrics which includes first and second state metrics, and first and second branch metrics. First and second offset values for the iteration are obtained. The first state and branch metrics are added together to obtain a first partial result. The second state and branch metrics are added together to obtain a second partial result. The second partial result is subtracted from the first partial result to obtain a difference. The first partial result and the first offset value are added together to obtain a first result. The second partial result and the second offset value are added together to obtain a second result. Either the first result or the second result is selected for output responsive to the difference. A log correction term is selected responsive to the difference.

Generating a log-likelihood ratio for signal processing

Address generation by an integrated circuit is described. An aspect relates generally to an address generator which has first and second processing units. The second processing unit is coupled to receive a stage output from the first processing unit and configured to provide an address output. The stage output is in a first range, and the address output is in a second range. The first range is from &#x2212;K to &#x2212;1 for K a block size, and the second range is from 0 to K&#x2212;1.

Address generation

A method and apparatus for the generation of discrete power series values (PSVs) and associated PSV addresses. Repeated evaluations of a discrete power series are performed by a reduced complexity PSV generator, such that the need for multiplication operations is obviated. Each evaluation cycle performed by the reduced complexity PSV generator is modified by each primitive root of the desired discrete power series. For each PSV generated, a corresponding address is calculated to indicate the correct placement of the PSV generated.

Method and apparatus for a discrete power series generator

An Add-Compare-Select circuit for use with a trellis decoder can include a first module and a second module. The first module can provide a difference signal specifying an indication of a difference between a second path cost and a first path cost of a trellis. The second path cost can be a sum of a second state cost and a second branch metric and the first path cost can be a sum of a first state cost and a first branch metric. The second module can select the first path cost or the second path cost as a new cost according to the difference signal of the first module.

Add-compare-select structures using 6-input lookup table architectures

A Turbo Code decoder for implementation in an integrated circuit is described. An add-compare select ('ACS') unit is configured to provide a difference between first and second outputs and to select one of the first and second outputs responsive to a difference thereof. An initialization stage is coupled to receive and configured to store for example the first output selected as an initialization value. A second select stage is coupled to receive for example the first output selected from the first select stage and coupled to obtain the initialization value stored from the initialization stage. The second select stage is configured to output either the first output selected from the ACS unit or the initialization value from the initialization stage.

Decoder for a turbo code

A circuit for a multi-channel add-compare-select unit is disclosed. The circuit includes a compare unit and a datapath. The datapath is coupled to the compare unit, and includes a number of adder units, a selection unit (which is coupled to the adder units), and a number of clocked storage stages.

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Lauder, United Kingdom

David I Lawrie