Data General Corporation

David I Epstein

Mark Douglas Hummel

James Marriot Guyer

David L Keating

Kenneth D Holberger

Charles J Holland

Steven J Wallach

Paul J Reilly

Josh Rosen

James E Veres

Paul W Woodbury

Donald C Wiser

Eric H Enberg

Leo C Waible, Iii

Rona J Newmark

Michael A Pogue

Harold R Kimmens

Peter C Bixby

Morgan J Dempsey

Rosemarie Alicandro

Donald D Burn

Shreyaunsh R Shah

Paul K Marino

Jeffrey F Hatalsky

Walker Anderson

Thomas J Myer

Patrick J Weiler

A method of assigning priorities and resolving bus contention in a distributed computer system is disclosed. Each system node is assigned an identifier. Priorities are reassigned at each change in bus access such that the node that most recently had access to the bus is assigned the lowest priority with the node having the next identifier in sequence being assigned the highest priority and all other nodes assigned priority in accordance with their identifier's position in the sequence. The identifiers are logically treated as organized in a circular fashion such that the lowest node identifier is considered to come next in the sequence after the highest node identifier.

Contention revolution in a digital computer system

Apparatus and method is disclosed for controlling the timing of the addressing, fetching and executing of microinstructions in a data processing system such that delayed sequencing microinstructions, stretched delayed sequencing microinstructions and immediate sequencing microinstructions may be intermixed in the microinstruction stream. Circuitry is provided to determine the type of sequencing specified for each microinstruction and control the generation of the execution cycle signal and the microinstruction address clocking signal such that these signals occur in the appropriate time sequence to accomplish the specified sequencing.

Microcode control apparatus

A data processing system in which macroinstructions are decoded to provide a sequence of microinstructions comprising one or more microroutines. If a fault condition occurs, the currently executing microinstruction of a sequence thereof is interrupted, while the fault is being handled. When the fault has been resolved, execution of the interrupted microinstruction resumes. If the fault cannot be resolved the sequence of microinstructions is permanently aborted. The process of interrupting the sequence and resuming operation at the interrupted microinstruction is essentially invisible to the microprogram.

Microsequencer for a data processing system using a unique trap handling

A data processing system in which macroinstructions are decoded to provide a sequence of microinstructions comprising one or more microroutines. A stack storage means stores data for use in such microroutines. The final microinstruction of the microroutines is a request to retrieve or remove data from the stack. When no data is present therein (the stack is empty) a new macroinstruction is requested and when data is present in the stack the microroutine returns to another mircoroutine in which it is acting as a micro-subsroutine to permit continuation of the other microroutine.

Microsequencer in a data processing system using stack storage for

Method and apparatus for improving instruction decoding in a microcode-controlled digital computer system. The microinstruction sequences are made simple and compact enough that sufficient complexity is required in the instruction decoding logic that it is feasible to custom-configure a gate array to perform instruction decoding. The resultant gate array, by virtue of being embodied in a single integrated circuit, is extremely fast and compact and has low power requirements.

Digital computer having unique instruction decoding logic

A data processing system having separate kernel, vertical and horizontal microcode, separate loading of vertical microcode and a permanently resident kernel microcode, and a soft console with dual levels of capability. The system includes a processor having dual ALC and microcode processors, and an instruction processor. Also included are a processor incorporating a multifunction processor memory, a malfunction nibble shifter, and a high speed look-aside memory control.

Method and apparatus for enhancing the operation of a data processing

A data processing system having separate kernel, vertical and horizontal microcode, separate loading of vertical microcode and a permanently resident kernel microcode, and a soft console with dual levels of capability. The system includes a processor having dual ALC and microcode processors, and an instruction processor. Also included are a processor incorporating a multifunction processor memory, a multifunction nibble shifter, and a high speed look-aside memory control. Adaptive microcode control means 272 are disclosed in which microinstruction sequencing is a function 273 of the current microinstruction and current machine state.

Data processing system with unique microcode control

A data processing uses instructions which may refer to operands in main memory by either physical or logical addresses. The central processor has an internal memory organized as two portions. The first portion provides a scratchpad memory function for the central processor and the second portion is responsive to logical addresses to provide corresponding physical addresses.

Digital data processing system having dual-purpose scratchpad and

A data processing system which handles thirty-two bit logical addresses which can be derived from either sixteen bit logical addresses or thirty-two bit logical addresses, the latter being translated into physical addresses by unique translation means. The system includes means for decoding macro-instructions of both a basic and an extended instruction set, each macro-instruction containing in itself selected bit patterns which uniquely identify which type of instruction is to be decoded. The decoded macro-instructions provide the starting address of one or more micro-instructions, which address is supplied to a unique micro-instruction sequencing unit which appropriately decodes a selected field of each micro-instruction to obtain each successive micro-instruction. The system uses hierarchical memory storage using eight storage segments (rings), access to the rings being controlled in a privileged manner according to different levels of privilege. The memory system uses a bank of main memory modules which interface with the central processor system via a dual port cache memory, block data transfers between the main memory and the cache memory being controlled by a bank controller unit.

Data processing system having a unique micro-sequencing system

Growing community of inventors

Framingham, MA, United States of America

David I Epstein