Other

David I Dalton

Alfred P Gnadinger

A snowboard trainer (SBT) includes an SBT platform, a slide rail, slide supports, a central stand, and a front interface. The slide rail extends from a first end to a second end. The slide supports connect the slide rail to the SBT platform. The slide supports are configured to support the slide rail relative to the SBT platform. The central stand is positioned relative to the slide rail on the SBT platform and positioned between the first end and the second end of the slide rail. The central board receiver is connected to the central stand. The front interface is configured to be secured to a front portion of a snowboard. The front interface includes a roller bearing sized to be retained in the central board receiver such that when the roller bearing is received in the central board receiver, the front interface three-dimensionally rotates relative to the central stand.

Snowboard trainer

A nonvolatile semiconductor memory device is described where each memory cell is composed of a single field effect transistor with a dual gate dielectric comprising a dielectric interfacial layer in contact with a silicon substrate and a ferroelectric layer in between the interfacial layer and the gate electrode. To program (write) the cell the ferroelectric layer is polarized in one of two directions, the ferroelectric polarization creating a large electric field in the interfacial layer. This electric field causes electrons or holes to be transported across the interfacial layer and be trapped in the ferroelectric layer establishing a high (erased) or low (programmed) threshold voltage depending on the direction of the ferroelectric polarization representing the two logic states. To read the memory cell a voltage is applied to the drain of the selected transistor and depending on whether a high or low threshold state was programmed into the cell a low or high current is sensed.

Single transistor charge transfer random access memory

A system and method for regulating the erase saturation in a semiconductor memory is disclosed. More particularly, the present invention measures the under-erase and over-erase condition of all SONOS transistors in an array of non-volatile SRAM cells and corrects the erase voltage to prevent over-erase and under-erase.

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Colorado Springs, CO, United States of America

David I Dalton