Advanced Micro Devices Corporation

Sun Microsystems, Inc.

David Hugh McIntyre

Alexander W Schaefer

Stephen Victor Kosonocky

Rahul Kumar Agarwal

Milind S Bhagavat

John J Wuu

Russell J Schreiber

Krishnan V Ramani

Raymond A Heald

Prasant Kumar Vallur

Ramon Mangaser

Jimmy Lee Reaves

Chitresh Chandra Narasimhaiah

Srikanth Reddy Gruddanti

Ravi T Jotwani

Gurupada Mandal

Suresh Seshadri

Manoj N Kulkarni

Samiul Haque Khan

William Y Mo

Deepika Kapil

Mandeep Singh

Hung Phuong Ngo

The disclosed device includes a data path having multiple transmission drivers. The device also includes a controller that is configured to tune each of the transmission drivers to a signal speed of a reference transmission driver. Various other methods, systems, and computer-readable media are also disclosed.

Data lane variation compensation for data rate enhancement

A data processor is implemented as an integrated circuit. The data processor includes a processor die. The processor die is connected to an integrated voltage regulator die using die-to-die bonding. The integrated voltage regulator die provides a regulated voltage to the processor die, and the processor die operates in response to the regulated voltage.

Multiple-die integrated circuit with integrated voltage regulator

A system and method for efficient power, performance and stability tradeoffs of memory accesses under a variety of conditions are described. A system management unit in a computing system interfaces with a memory and a processing unit, and uses boosting of word line voltage levels in the memory to assist write operations. The computing system supports selecting one of multiple word line boost values, each with an associated cross-over region. A cross-over region is a range of operating voltages for the memory used for determining whether to enable or disable boosting of word line voltage levels in the memory. The system management unit selects between enabling and disabling the boosting of word line voltage levels based on a target operational voltage for the memory and the cross-over region prior to updating the operating parameters of the memory to include the target operational voltage.

Programmable write word line boost for low voltage memory operation

A dynamic NOR circuit includes a pre-charge transistor coupled between a first voltage supply node and a dynamic node to pre-charge the dynamic node. The dynamic NOR circuit includes a first keeper circuit having a first keeper transistor and a second keeper transistor serially coupled between the first voltage supply node and the dynamic node. The dynamic NOR circuit includes a first pull down circuit coupled between the dynamic node and ground. A first input signal is coupled to a gate of a first pull-down transistor in the first pull-down circuit and is also coupled to a gate of the first keeper transistor. A first keeper enable signal is coupled to a gate of the second keeper transistor. Additional keeper circuits and pull down circuits coupled to the dynamic node allow the dynamic NOR structure to handle a plurality of input signals.

Contention-free dynamic logic

A method and an apparatus for power filtering in a Translation Look-aside Buffer (TLB) are described. In the method and apparatus, power consumption reduction is achieved by suppressing physical address (PA) reads from random access memory (RAM) if the previously translated linear address (LA), or virtual address (VA), is the same as the currently requested LA. To provide the correct translation, the output of the TLB is maintained if the previously translated LA and the LA currently requested for translation are the same.

Power filter in data translation look-aside buffer based on an input linear address

A method and a processor load/store unit (LSU) are described for performing store-to-load forwarding (STLF) from an interlocking store. STLF is performed when a starting address of the store and the load do not match, or when a data size of the store is smaller than a data size of the load. The LSU detects a load that interlocks with a store, and determines whether all or only a portion of data bytes needed by the load can be provided by the interlocking store. If it is determined that only a portion of the data bytes needed by the load can be provided by the interlocking store, then that portion of the data bytes is provided by a store data buffer (SDB) and the remaining portion of the data bytes needed by the load is provided by a data cache (DC). Otherwise, the SDB provides all of the data bytes.

Method and apparatus for performing store-to-load forwarding from an interlocking store using an enhanced load/store unit in a processor

A conditionally precharged content addressable memory (CAM) includes forcing a mismatch on a matchline of the CAM if a data entry in the CAM is invalid. The matchline of the CAM is precharged only if the data entry is valid.

Conditionally precharged dynamic content addressable memory

A multi-port memory array is disclosed. The memory array includes a plurality of memory subblocks and an output network. Each memory subblock includes a plurality of single-read-port memory cells. The output network is configured to redirect information read for a first read port to a second read port on a condition that an equivalence signal indicates that read addresses for the first read port and the second read port are the same. The latching and multiplexing operation may be integrated. The memory cells may be 6-transistor synchronous random access memory (SRAM) cells, 8-transistor SRAM cells, or any type of memory cells.

Multi-port memory array

An improved circuit for sensing and programming fuses in integrated circuits. The circuit is broadly comprised of a fuse cell, a reference circuit, a sense amplifier and a level detector. In one embodiment of the present invention, a two-stage sensing scheme is implemented. The improved fuse sensing circuit uses current-mode sensing and implements an auto-read current reduction scheme. Using a level-detect circuit, the virtual ground is raised automatically if the high-voltage power supply exceeds core supply (Vdd) by a fixed dc voltage. This reduces effective sensing voltage and the read current and thus helps preserve unblown fuse integrity. In one embodiment of the invention, four modes of operation are implemented: 'Normal Read,' 'Unblown_Read,' &#x201c;Blown_Read_1&#x201d; and &#x201c;Blown_Read_2.&#x201d; The default read mode is the &#x201c;normal read&#x201d; while the &#x201c;Unblown&#x201d; and &#x201c;Blown&#x201d; read modes are for fuse calibration purposes. In the &#x201c;Unblown_Read&#x201d; read mode, the circuit is operable to compare the fuse resistance against a lower reference resistance, closer to an unblown fuse resistance value, in order to make the comparison more stringent. Similarly, the &#x201c;Blown_Read_1&#x201d; and &#x201c;Blown_Read_2&#x201d; modes allow a more stringent comparison for a blown fuse resistance.

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Sunnyvale, CA, United States of America

David Hugh McIntyre