International Business Machines Corporation

David Hom

Elpida Tzortzatos

Scott B Tuttle

Harris M Morgenstern

Robert Miller, Jr

Paula M Spens

Charles E Mari

Steven M Partlow

Matthew J Mauriello

Alfred F Foster

Michael Gary Spiegel

Mariama Ndoye

Chun-Kwan K Yee

Donald W Schmidt

Peter Grimm Sutton

James H Mulder

Karl David Schmitz

Peter A Fatzinger

Dynamic memory area configuration includes designating a portion of memory as a specialized memory unit, and reserving a first portion of specialized memory unit for a plurality of page frame table entries (PFTEs) representing a plurality of frames in the specialized memory. One or more of the PFTEs are stored in respective queue entries within a queue in a reserved area of the specialized memory unit. A particular queue entry indicates that a particular PFTE associated with a particular frame is available for use. An offline request to take a second portion of the specialized memory unit offline is received. Whether to fulfill the offline request is determined based on whether the second portion of the specialized memory unit has an associated queue entry within the queue indicating that the associated frame is not in use back a portion of a page frame table (PFT) or the specialized memory unit.

Dynamic memory area configuration for building page frame table entries

Technical solutions are described for reducing page invalidation broadcasts in a computer system. An example method includes pre-allocating a pool of large memory frames by a real storage manager. The method also includes receiving, by a virtual storage manager, an instruction from an application to allocate a memory buffer, where the instruction includes a request to back the memory buffer using large pages. The virtual storage manager, in response to the instruction, allocates the memory buffer from the pre-allocated pool of large memory frames.

Reducing page invalidation broadcasts

Embodiments are provided for implementing a transparent conversion of common virtual storage requests to storage with limited access. Embodiments include providing a storage manager configured to perform address translation for requests, providing a data address translation (DAT) structure configured to connect a higher-level DAT table to a lower-level DAT table, and creating the DAT structure based on a request from a process. Embodiments also include responsive to receiving a storage request, performing a DAT fault process based on validating user credentials associated with an entry of the higher-level DAT table corresponding to the storage request, and responsive to the validation, updating the higher-level DAT table entry to allow access to the restricted-use portion of the common virtual storage, and otherwise, returning a DAT fault for the higher-level DAT table entry.

Transparent conversion of common virtual storage

A method, a computer program product, and a system for performing a batch processing are provided. The batch processing includes initializing a set of elements corresponding to a set of resources to produce an initialized group and chaining the initialized group to previously initialized elements to produce an element batch, when the previously initialized elements are available. The batch processing further includes setting a system lock on the set of resources after the element batch is produced; executing a service routine to move the element batch to a queue by referencing first and last elements of the element batch; and releasing the system lock on the set of resources once the service routine is complete.

Optimizing the initialization of a queue via a batch operation

In one embodiment, a computer-implemented method includes building an available frame header queue (AFHQ). The AFHQ includes one or more headers, each header including one or more frame references being no more than a maximum count of frame references. Each of the one or more frame references of each of the one or more headers refers to an available frame. A frame request is received for one or more requested frames. One or more frame references are extracted, by a computer processor, from the AFHQ in response to the frame request. The extracting includes extracting from the AFHQ one or more requested headers including the one or more frame references referring to at least a portion of the one or more requested frames.

Available frame queue processing

Technical solutions for providing real time analytics of a private area of a virtual address space are described. One general aspect includes a method that includes determining, by a processor, a start address and a size of the private area of the virtual address space. The method also includes determining, by the processor, a highest address corresponding to a user region of the private area. The method also includes determining, by the processor, a lowest address corresponding to a high-end region of the private area. The method also includes storing, by the processor, the determined information in a common area outside the virtual address space.

Virtual storage instrumentation for real time analytics

A computer system includes a translation look-aside (TLB) buffer and a processing unit. The TLB is configured to store an entry that comprises virtual address information, real address information associated with the virtual address information, and additional information corresponding to at least one of the virtual address information and the real address information. The processing unit is configured to control the TLB to modify the additional information while maintaining the entry in a valid state accessible by the processing unit for a translation look-aside operation corresponding to the virtual address information and the real address information.

Translation look-aside table management

A fault occurs in a virtual environment that includes a base space, a first subspace, and a second subspace, each with a virtual address associated with content in auxiliary storage memory. The fault is resolved by copying the content from auxiliary storage to central storage memory and updating one or more base space dynamic address translation (DAT) tables, and not updating DAT tables of the first and second subspace. A subsequent fault at the first subspace virtual address is resolved by copying the base space DAT table information to the first subspace DAT tables and not updating the second subspace DAT tables. A fault occurring with association to the virtual address of the first subspace is resolved for the base space and the base space DAT table information is copied to the first subspace DAT tables, and the second subspace DAT tables are not updated.

Resolving memory faults with reduced processing impact

Embodiments of the disclosure include a method for reserving large pages in a large frame area (LFAREA) of a main memory. The method includes pre-scanning a plurality of storage increments and counting a number of available large pages that are online and issuing a message that indicates the number of available large pages. The method also includes receiving and parsing an LFAREA request including a target number of large pages to be reserved. The method further includes calculating an optimal number of large pages to be reserved, based upon the target number of available pages and a system limit. The method includes determining if the LFAREA request is valid and if the LFAREA request can be satisfied and scanning the plurality of the storage increments and reserving the optimal number of pages in the LFAREA.

Reserving fixed page areas in real storage increments

Dedicated large page memory pools are provided to, at least in part, facilitate access to large pages. The large page memory is managed by: establishing multiple large page memory pools, each large page memory pool of the multiple large page memory pools including a number of large pages; and dedicating each large page memory pool of the multiple large page memory pools to a respective processor of multiple processors of the computing environment, wherein processors of the multiple processors can concurrently access pages from the respective large page memory pools of the multiple large page memory pools.

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Poughkeepsie, NY, United States of America

David Hom