Avago Technologies General IP (singapore) Pte. Ltd.

David Hartzell Leebrick

Osvaldo Buccafusca

Jim Roland

A process control monitor for determination of alignment between layers of a semiconductor structure includes a patterned layer having a plurality of lines formed on a base layer, the plurality of lines enclosed within a circle. A photo-resist layer is deposited on top of the base layer and over the patterned layer. The photo-resist layer may be patterned to include an opening that exposes a portion of the base layer adjacent the patterned layer and that exposes a portion of the patterned layer. Alignment between the patterned layer and the patterned photo-resist layer may be determined according to a contrast between the exposed portion of the base layer and the exposed portion of the patterned layer.

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Fort Collins, CO, United States of America

David Hartzell Leebrick