Advanced Micro Devices Corporation

Advance Micro Devices, Inc.

David Harry Eppes

Michael R Bruce

Rosalinda M Ring

Victoria Jean Bruce

Brennan V Davis

Glen P Gilfeather

Daniel L Stone

Srikar V Chunduri

Thomas J McKeone

Rama Rao Goruganthu

Paiboon Tangyunyong

Arnold Y Louie

Charles F Hawkins

Richard Jacob Wilcox

Jason Mulig

Michael Zhuoying Su

Edward I Cole, Jr

Various methods of mounting semiconductor chips on a substrate are disclosed. In one aspect, a method of manufacturing is provided that includes coupling a first plurality of solder interconnect structures to a first semiconductor chip. The first solder interconnect structures have a first melting point. The first semiconductor chip may be tested. If the first semiconductor chip passes the testing, then a second semiconductor chip is coupled to the first semiconductor chip using a second plurality of solder interconnect structures that have a second melting point lower than the first melting point.

Variable temperature solders for multi-chip module packaging and repackaging

A technique for improving the thermal power dissipation of an integrated circuit includes reducing the thermal resistivity of the integrated circuit by increasing heat transfer in vertical and/or lateral directions. These results are achieved by increasing the surface area of the backside and/or the surface area of the lateral sides of the integrated circuit die. In some embodiments of the invention, an integrated circuit includes circuit elements formed closer to a first surface of a semiconductor substrate than to a second surface of the semiconductor substrate. The semiconductor substrate has a varying profile that substantially increases the surface area of a thermal interface formed on the second surface as compared to the second surface being substantially planar. A maximum depth of the profile is less than the thickness of the semiconductor substrate.

Integrated circuit with increased heat transfer

A method and structure prevents crack propagation to the active die circuitry of a main die area during sawing around the outer periphery of the main die area. Stress relief elements, such as dummy vias, are provided in the scribe line area between the saw lane and the main die area. The dummy vias prevent cracks induced by the sawing process from propagating to the main die area.

Crack resistant scribe line monitor structure and method for making the same

Defect analysis of an integrated circuit die having a back side opposite circuitry at a circuit side and a liquid crystal liquid is enhanced using near infrared (nIR) laser light. According to an example embodiment of the present invention, nIR laser light is directed to an integrated circuit die having a liquid crystal layer formed over the die. When the die includes a defect that generates heat, the heat generated in the die as a result of the nIR laser light adds to the heat in the die generated as a result of the defect and causes a portion of the liquid crystal layer to change phase near the defect. The phase change is detected and used to identify a portion of the die having a defect.

Integrated circuit defect analysis using liquid crystal

Semiconductor die analysis is enhanced via a method and system that use a heater having a plurality of heating elements to heat a selected portion of the die. According to an example embodiment of the present invention, the heater is thermally coupled to the die, and the die is operated while at least one of the plurality of heating elements heats a portion of the die. A response is detected and used to analyze the die. The present invention makes possible selective heating of the die in a manner that is readily controllable and implemented. Die analysis, including, for example, critical timing path analysis, is enhanced by this ability to controllably heat the die.

Integrated circuit heating system and method therefor

Analysis of a semiconductor die is enhanced by the stimulation the die and the detection of a response to the stimulation. According to an example embodiment of the present invention, a semiconductor die is analyzed using indirect stimulation of a portion of the die, and detecting a response therefrom. First, selected portion of circuitry within the die is stimulated. The stimulation of the selected portion induces a second portion of circuitry within the die to generate an external emission. The emission is detected and the die is analyzed therefrom. In one particular implementation, a response from the selected portion is inhibited from interfering with the detection of the emission from the second portion of circuitry.

Indirect stimulation of an integrated circuit die

The operability of light-based semiconductor die analysis is enhanced using a method and arrangement that directs light between a light source and a die. In one example embodiment of the present invention, a light source is directed to a die in a semiconductor analysis arrangement using a fiber optic cable. The analysis arrangement is adapted to use light received via the fiber optic cable to analyze the die. The analysis includes one or more light-based applications, such as stimulating a selected portion of the die with the light and detecting a response therefrom. In this manner, light can be directed to a die in a variety of analysis implementations, such as for analyzing a die in a test chamber.

Fiber optic semiconductor analysis arrangement and method therefor

A semiconductor device is analyzed and manufactured using a heat-exchange probe. According to an example embodiment of the present invention, a heat-exchange probe is controlled to exchange heat to a portion of a semiconductor device using sub-micron resolution. In one implementation, sub-micron resolution is achieved using a navigational arrangement, such as microscope, adapted to direct light to within about one micron of a target circuit portion on a plane of the device. In another implementation, a physical heat probe tip (e.g., a metal probe having about a one micron diameter probe tip) is navigated to a selected portion of the device using sub-micron navigational resolution. In each of these implementations, as well as others, the heat exchange is preponderantly confined to within about a one micron radius of a target portion of circuitry on lateral plane of the device. With this approach, heat exchange can be controlled to selectively stimulate circuitry within the device, which is particularly useful in high-density circuit implementations.

High resolution heat exchange

Substrate removal for analysis of a semiconductor die is enhanced via a method and system for heating the die. According to an example embodiment of the present invention, a plurality of heating elements are formed in a semiconductor die. The die is operated while at least one of the plurality of heating elements heats a portion of the die adjacent the heating element. A response to the heating is detected and used to analyze the die. The present invention makes possible selective heating of the die in a manner that is readily controllable and implemented. Die analysis, including, for example, critical timing path analysis, is enhanced by this ability to controllably heat the die.

Integrated circuit internal heating system and method therefor

The operability of light-based semiconductor die analysis is enhanced using a method and arrangement that can detect light leakage between a light source and a die. In one example embodiment of the present invention, a light source is directed to a semiconductor analysis arrangement using, for example, a fiber optic cable. The analysis arrangement is adapted to use light from the light source for analyzing the die. A light detection arrangement detects a condition of light leakage from the system and generates a signal representing the condition of light leakage. The generated signal can then be used to control the semiconductor analysis arrangement, such as by deactivating the light source in response to a detected leak, or by allowing the light source to function in response to not detecting a leak.

Semiconductor analysis arrangement and method therefor

Semiconductor die analysis is enhanced using a system that is adapted to perturb a die in a test chamber and to detect a response from the die to the perturbation. According to an example embodiment of the present invention, a semiconductor die analysis system includes a test chamber and a docking arrangement adapted to dock with the test chamber. A die is held in the docking arrangement and is presented inside of the test chamber when the docking arrangement is docked with the chamber. Two or more perturbation devices are used to perturb the die, and controller is adapted to control the perturbation. A data acquisition arrangement receives data from the die in response to the perturbation, and the data is used for analyzing the die.

Defect analysis of an integrated circuit die having an internal heat source is enhanced using a method and system that use the internal heat source to heat the die. According to an example embodiment of the present invention, a semiconductor die having a liquid crystal layer is analyzed by detecting a liquid crystal phase change caused by electrical operation of the die. A first circuit region is electrically operated and used as the primary heat source to generate sufficient heat at a second circuit region to effect a separately viewable phase change in an area of the liquid crystal layer corresponding to the second circuit region. The internal heat source is adapted to cause the liquid crystal phase change without necessarily heating the die with an external heat source. A detector is adapted and used to detect the liquid crystal phase change in the area corresponding to the second circuit region.

Defect detection using liquid crystal and internal heat source

Defect analysis of an integrated circuit die is enhanced using a method and system that make possible the detection of defect-related heat generation in the die. According to an example embodiment of the present invention, a semiconductor die having a liquid crystal layer is analyzed by detecting a liquid crystal phase change caused by heating the die. The heating causes a first circuit region and a second circuit region to effect a separate phase change in corresponding areas of the liquid crystal layer. A detector is adapted to use time-lapsed analysis to detect the liquid crystal phase change in the area corresponding to the second circuit region before the corresponding areas cease to be separately detectable.

Time-lapsed IC defect analysis using liquid crystal

A method and apparatus mechanism for testing data processing devices are implemented. The test mechanism isolates critical paths by correlating a scanning microscope image with a selected speed path failure. A trigger signal having a preselected value is generated at the start of each pattern vector. The sweep of the scanning microscope is controlled by a computer, which also receives and processes the image signals returned from the microscope. The value of the trigger signal is correlated with a set of pattern lines being driven on the DUT. The trigger is either asserted or negated depending the detection of a pattern line failure and the particular line that failed. In response to the detection of the particular speed path failure being characterized, and the trigger signal, the control computer overlays a mask on the image of the device under test (DUT). The overlaid image provides a visual correlation of the failure with the structural elements of the DUT at the level of resolution of the microscope itself.

Data processing device test apparatus and method therefor

Defect analysis of a flip chip die having a back side opposite circuitry at a circuit side and a liquid crystal layer is enhanced using a method and system that makes possible the detection of the defect from the back side of the flip chip. According to an example embodiment of the present invention, a flip chip die having a liquid crystal layer is analyzed by detecting a liquid crystal phase change caused by heat generation at a defect in the die. By detecting the phase change associated with a defect, the defect can be located. The defect detection can be used through the back side of the die, and can be used to detect defects located near intrinsic heat sources that make conventional liquid crystal analysis difficult or even impossible.

Growing community of inventors

Austin, TX, United States of America

David Harry Eppes