Texas Instruments Corporation

David Harold Bartley

Timothy J McEntee

Donald W Oxley

Jonathan F Humphreys

Reid E Tatge

Alan S Ward

Paul Fuqua

Hamid Rahim Sheikh

William M Johnson

Jonathan H Shiell

John W Glotzbach

Jeffrey L Nye

Rajendra K Talluri

Satish M Thatte

Shalini Gupta

Murali S Chinnakonda

Elana D Granston

Edward E Ferguson

Ajay Jayaraj

Toshio Nagata

Stephen Busch

Ganesh Sundararajan

Robert Jp Nychka

Traditionally, providing parallel processing within a multi-core system has been very difficult. Here, however, a system is provided where serial source code is automatically converted into parallel source code, and a processing cluster is reconfigured 'on the fly' to accommodate the parallelized code based on an allocation of memory and compute resources. Thus, the processing cluster and its corresponding system programming tool provide a system that can perform parallel processing from a serial program that is transparent to a user. Generally, a control node connected to the address and data leads of a host processor uses messages to control the processing of data in a processing cluster. The cluster includes nodes of parallel processors, shared function memory, a global load/store, and hardware accelerators all connected to the control node by message busses. A crossbar data interconnect routes data to the cluster circuits separate from the message busses.

Integrated circuit with control node circuitry and processing circuitry

A compiler tool is provided to selectively solicit assistance from a programmer in order to improve optimization of code compiled by the compiler. As a program is being compiled, the compiler keeps track of the places where it could do better if it only knew certain information. The user is presented with one or more pieces of advice that each identify a problem that prevented the compiler from making a particular optimization due to not enough information and one or more suggestions as to how to provide additional information to the compiler. This list is generally filtered so that only a subset of missing information that has a high likelihood of leading to better performance is presented. Other missing information is not requested.

Method for selective solicitation of user assistance in the performance tuning process

A method of generating profiled optimized code using user interface () that allows a user to visually understand, inspect, and manipulate a compiled application program as a function of compiler options, such as, code size and speed, is provided. A program () is compiled in a compiler () with two or more compiler options such as size and speed and the resulting executables () are profiled (). The results of the profiles () are analyed in a solver () for generating sets of useful solutions () wherein the sets have methods of compiling at the function level. The useful solutions () are displayed () at the user interface () to allow the user to visually understand, inspect and manipulate compiler options to select compiler options () for the program.

Method of generating profile-optimized code

A user interface that allows a user to visually understand, inspect, and manipulate a compiled application program as a function of compiler options, such as, code size and speed, is provided.

User interface for making compiler tradeoffs

A system ( ) for compressing video information includes an image detector ( ) generating image information regarding a selected scene, a supplemental detector ( ) generating supplemental information regarding the scene which is different from the image information, and a processing section ( ). The processing section generates compressed information by processing the image information as a function of the supplemental information. The processing section may store the compressed information in a storage section ( ), or may transmit the compressed information to a remote device through a communication link ( ). The image detector may generate video images of the scene in response to visible light. The supplemental detector may generate images of the scene which represent heat or distance, or may determine the portion of the scene to which an eye ( ) of an operator is directed.

Compression of information from one detector as a function of information from another detector

This invention is a very long instruction word data processor including plural data registers, plural functional units and plural program counters and is selectively operable in either a first or second mode. In the first mode, the data processor executes a single instruction stream. In the second mode, the data processor executes two independent program instruction streams simultaneously. In the second mode the data processor may respond to two instruction streams accessing only corresponding halves of the data registers and function units. Alternatively, the data processor may respond to a first instruction stream including instructions referencing the whole data processor employing A side function units by alternatively dispatching (1) instructions referencing the A side data registers and the A side function units and (2) instructions referencing the B side data registers and the B side function units. In the first mode, the data processor fetches N bits of instructions each cycle. In the second mode the data processor may fetch N bits of instructions for alternate program counters on alternate cycles or fetches N/2 bits of each of the first and second program counters. The data processor includes interrupt steering and masking control logic allowing instructions to control whether the first instruction stream or the second instruction stream receives interrupts.

Dual-mode VLIW architecture providing a software-controlled varying mix of instruction-level and task-level parallelism

A method of optimizing a computer program for reduced power consumption by a processor (,) having functional units (,) that are independently controllable by instructions. The processor's instruction set (FIG.,) has instructions that may be directed to a particular functional unit (,) so as to place that functional unit in a power-down state while not being used during a program segment.

Power reduction for processors by software control of functional units

Generally, in one form of the invention, a computer system for executing application programs in hard real-time, comprises a central processing unit (CPU) for executing the application programs and system programs and a computer memory partitioned into a data memory and a code memory. A garbage collector, which executes on said CPU, places a write barrier over certain portions of memory. Furthermore, it transfers an object from a location in the memory to a second object at another location in the memory. In a critical section, which may not be interrupted, it allocates sufficient space for the second object so that the entire contents from the first object can be copied into the second object, and in an interruptable section, it copies the entire contents of the first object into the second object. A write routine is linked into the application programs for updating objects in the computer memory. The write routine is operable to update both the first object and the second object whenever the garbage collector is transferring the contents of the object into the second object. Both copies are thereby kept current.

System and method for hard real-time garbage collection requiring a

A pointer, N, indicates an address in a virtual memory space of a demand paged memory including a plurality of virtual address pages and a fixed number of physical memory pages into which blocks of information can be written. A back-up memory store is provided for containing paged-out memory pages. The pointer, N, is advanced along the virtual address pages to indicate the next available virtual address page for allocation, and newly allocated blocks are located on the virtual address page pointed to by said pointer N. Should the necessary space for a block allocation not exist on the page pointed to by said pointer, N, a page which is most recently used and least sparsely utilized is identified from the physical pages onto which blocks have been previously written the block is allocated on that page. If no space remains on the virtual address pages in physical memory for block allocation, then, a least recently used and most sparsely allocated page is identified and paged-out to the back-up store.

Method for managing virtual memory to separate active and stable memory

A reference count decimator and method of operating a computer system includes a decimator queue for containing indications of pointer reference count increments. Apparatus is provided for determining if a referencing event would cause a decrement of a reference count, and for searching the decimator queue to determine if a counterpart of the reference event exists in the queue, to thereby define an increment/decrement pair. If an increment/decrement pair is determined to exist in the queue, the increment/decrement pair is cancelled from the queue so that the increment/decrement point reference pairs are removed from the computer system without actually modifying the reference count indications associated with the memory blocks.

Apparatus and method removing increment/decrement pairs to decimate a

A method for compacting blocks of memory in a demand paged virtual address space which includes a plurality of virtual address pages includes identifying active and stable blocks to be compacted by defining a pointer to indicate a page of the virtual memory space, and advancing the pointer to continually indicate the page of the beginning of the available virtual memory space. As new blocks are allocated, they are located in the virtual address space beginning at the next available location of the advancing pointer. As blocks are referenced by the user, they are moved to the current location of the advancing pointer, so that, stable blocks may be collected together on stable pages and active blocks are collected together on active pages. A disk memory is provided, and periodically the pages containing collected stable blocks are 'paged-out' to it. The method improves the overall throughput of data in the memory by reducing the time waiting for disk, the time in which the CPU is delayed during frequent garbage collections, and the allocation response time. Also, the method insures efficient use of the backing store by insuring that sparsely allocated pages are not written out to disk.

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Dallas, TX, United States of America

David Harold Bartley