Analog Devices,inc.

David Hanrahan

John Blake

Kohji Yoshida

Matt Smith

An operating circuit ( ) for controlling the speed of a cooling fan motor ( ) for computer cabinetry ( ), and for determining an under-speed condition in the fan motor ( ) comprises a control circuit ( ) which controls a variable output signal generator circuit ( ) for outputting a pulse width modulated signal corresponding to the desired fan speed for switching a switching circuit ( ) in a power supply circuit of the fan motor ( ) for pulse width modulating the power supply to the fan motor ( ). A monitoring resistor (R ), a capacitor (C ) and a circuit ( ) provides a tachometer signal to the operating circuit ( ). A gate circuit ( ) gates the second and fourth pulses of the tachometer signal to a counter ( ) which counts clock pulses from a clock signal generating circuit ( ) between the rising edges of the second and fourth pulses which are in turn stored in a register ( ) for comparison with a reference count by a comparator ( ). The comparator ( ) outputs an alert signal in the event of the count in the register ( ) exceeding the reference count indicating under-speed of the fan. The control circuit ( ) controls the signal generator circuit ( ) for holding the pulse width modulated signal outputted to the switching circuit ( ) on during a duty cycle between the rising edges of the second and fourth pulses of the tachometer signal so that the tachometer signal remains available until the fan speed has been determined.

Method and apparatus for determining fan speed

A system for a providing addresses to each one of a plurality of addressable integrated circuits. The system includes a plurality of address select circuits, each one thereof being coupled to a corresponding one of a corresponding plurality of addressable integrated circuit. Each one of such integrated circuits has an address select pin adapted to receive a signal from the corresponding one of the address select circuits. The signal is indicative of an address for such one of the plurality of addressable integrated circuits. Each one of such address circuit includes a signal source connected to the pin and a circuit for coding such signal source into a selected one of more than three predetermined signal levels. The integrated circuit includes a converter for converting such selected one of the signal levels into a address signal for such one of the integrated circuits during an initial address select mode and for providing conversion of a second signal in the integrated circuit for use by such integrated circuit in processing the second signal fed to such integrated circuit during a subsequent normal operating mode. In one embodiment the converter is an analog to digital converter. The other signal is indicative of temperature. A register is provided for storing the address signal for such one of the integrated circuits.

Growing community of inventors

Waterford, Ireland

David Hanrahan