Analog Devices,inc.

David Hall Whitney

Javier Alejandro Salcedo

Chau Cuong Tran

Adrian P Brokaw

Kimo Y F Tam

Stefano I D'Aquino

JoAnn P Close

Jennifer W Pierdomenico

Iliana Fujimori Chen

Moshe Gerstanhaber

Rikky Muller

Apparatus and methods to increase the range of a signal processing circuit. A system uses floating bias circuits coupled to a signal processing circuit to increase the range of power supplies that can be used with the signal processing circuit, while maintaining the components of the signal processing circuit within a breakdown voltage threshold. As the voltage level of the data signal varies, the voltage level of the floating bias circuits varies as well.

Circuits with floating bias

Apparatus and methods for electronic circuit protection under high stress operating conditions are provided. In one embodiment, an apparatus includes a substrate having a first p-well, a second p-well adjacent the first p-well, and an n-type region separating the first and second p-wells. An n-type active area is over the first p-well and a p-type active area is over the second p-well. The n-type and p-type active areas are electrically connected to a cathode and anode of a high reverse blocking voltage (HRBV) device, respectively. The n-type active area, the first p-well and the n-type region operate as an NPN bipolar transistor and the second p-well, the n-type region, and the first p-well operate as a PNP bipolar transistor. The NPN bipolar transistor defines a relatively low forward trigger voltage of the HRBV device and the PNP bipolar transistor defines a relatively high reverse breakdown voltage of the HRBV device.

Methods for protecting electronic circuits operating under high stress conditions

A multi-channel circuit includes a first-channel circuit configured to receive a digital input and a second-channel output voltage, and to generate a first-channel output voltage as a function of the received digital input and second-channel output voltage.

High-accuracy multi-channel circuit

Apparatus and method for protection of electronic circuits operating under high stress conditions

A circuit includes a pair of input transistors configured as a differential pair and having input terminals configured to receive an input voltage. The circuit also includes a first current source connected to and configured to provide a first tail current to the pair of input transistors, the first tail current being a class-A current having a non-zero quiescent value. The circuit also includes a second current source connected to and configured to provide a second tail current to the pair of input transistors, the second tail current being a class-B current having a zero quiescent value and a non-zero non-quiescent value. The second current source is configured to provide the second tail current as a function of the input voltage.

Boosted tail-current circuit

A low quiescent power class AB current mirror circuit includes a first input transistor for receiving an input current and a second output transistor for providing an output current; the first and second transistors having bases connected together; and a first current supply for sinking current from the bases in response to a decrease in input current to lower the quiescent point of the transistors.

Low quiescent power class AB current mirror circuit

An Early voltage and beta current compensated cascode current mirror includes a cascode current mirror having an input stage responsive to an input current, a current mirror circuit having a first stage responsive to the input stage and a second stage responsive to the first stage, and an output stage responsive to the second stage for providing an output voltage and current; and a compensation circuit, responsive to the cascode current mirror, having a first compensation stage, a second compensation stage and a bootstrapping buffer, the first compensation stage, in response to a change in the output voltage, impressing a corresponding change in voltage on the second compensation stage, the second compensation stage thereby providing a change in current to the cascode current mirror for cancelling current errors induced by base current modulation in the output stage, the bootstrapping buffer, in response to the change in voltage, impressing a corresponding change in voltage on the first compensation stage to prevent errors from base current modulation effects in the first compensation stage, the first and second compensation stages further providing a base current to the cascode current mirror for cancelling base current errors in the output current induced by the cascode current mirror.

Early voltage and beta compensation circuit for a current mirror

An error compensated current mirror includes a current mirror circuit having an input transistor and an output transistor; a bias current source in series with the input transistor and a load current source in series with said output transistor; the load current source including a load current source transistor in series with a load current source impedance; an input terminal connected between the bias current source and the input transistor; a buffer circuit including a transistor having its base connected between the load current source and the output transistor; a buffer biasing current source connected in series with the buffer circuit, the buffer biasing current source including a buffer biasing current source transistor in series with a buffer biasing current source impedance; said buffer biasing current source transistor being a replica device of the output transistor; an output terminal connected between the buffer circuit and the buffer biasing current source; and a compensating circuit including a compensator transistor having its base tied to the base of the buffer biasing current source transistor, its emitter connected between the buffer transistor and the buffer biasing current source impedance and its collector connected between the load current source impedance and the load current source transistor for driving the load current source to supply a current to the output transistor which is matched to that demanded by the buffer biasing current source transistor.

Growing community of inventors

Westford, MA, United States of America

David Hall Whitney