Micron Technology Incorporated

Ovonyx Memory Technology, LLC

Other

Aptina Imaging Corporation

Round Rock Research, LLC

David H Wells

H Montgomery Manning

Mirzafer K Abatchev

Jun Liu

Eric J Knappenberger

John J Michiels

Sanh D Tang

Whonchee Lee

Janos Fucsko

Kanwal K Raina

James J Alwan

Paolo Tessariol

Aaron R Wilson

Baosuo Zhou

Krupakar Murali Subramanian

Gurtej S Sandhu

Kunal Shrotri

James J Hofmann

Anish A Khandekar

Jie Li

Du Li

Christopher D Cardon

Caner Onal

David A Cathey

David A Zimlich

Tuman Earl Allen, Iii

Eric Blomiley

Umberto Maria Meotto

Patrick M Flynn

Durai Vishak Nirmal Ramaswamy

John David Hopkins

Luan C Tran

Roy Edward Meade

Michael P Violette

Darwin A Clampitt

Lifang Xu

Rita J Klein

Lorenzo Fratin

Richard J Hill

John Mark Meldrim

Indra V Chary

Zengtao T Liu

Stephen W Russell

Yushi Hu

Enrico Varesi

Paolo Fantini

Song Guo

Jianping P Yang

Ji Ung Lee

Kevin Y Titus

Yoshiaki Fukuzumi

Kirk D Prall

John K Zahurak

Kamal M Karda

Ulrich C Boettiger

F Daniel Gealy

Bhaskar Srinivasan

Emilio Camerlenghi

Kevin W Tjaden

Lars P Heineck

Matthew S Thorum

Shane P Leiphart

Harsh Narendrakumar Jain

Marko Milojevic

A three-dimensional variable resistance memory array and method of forming the same. The memory array has memory cells in multiple planes in three dimensions. The planes of the memory cells include shared interconnect lines, dually connected to driving and sensing circuits, that are used for addressing the cells for programming and reading. The memory array is formed using only a single patterned mask per central array plane to form the memory cells of such planes.

Method and apparatus providing multi-planed array memory device

Methods, systems, and devices for sparse piers for three-dimensional memory arrays are described. A semiconductor device, such as a memory die, may include pier structures formed in contact with features formed from alternating layers of materials deposited over a substrate, which may provide mechanical support for subsequent processing. For example, a memory die may include alternating layers of a first material and a second material, which may be formed into various cross-sectional patterns. In some examples, the alternating layers may be formed into one or more pairs of interleaved comb structures. Pier structures may be formed in contact with the cross sectional patterns to provide mechanical support between instances of the cross-sectional patterns, or between layers of the cross-sectional patterns (e.g., when one or more layers are removed from the cross-sectional patterns), or both.

Sparse piers for three-dimensional memory arrays

Methods, systems, and devices for dense piers for three-dimensional memory arrays are described. In some examples, a memory device may include pier structures formed in contact with features formed from alternating layers of materials deposited over a substrate. For example, a memory device may include alternating layers of a first material and a second material. In some examples, the alternating layers may be formed into a pair of interleaved comb structures. Pier structures may be formed in contact with the cross sectional patterns, and may provide mechanical support of cross-sectional pattern of the remaining material. In some examples, the piers may further act as a separator between memory cells or other features of the memory device. For example, the piers may extend into at least a portion of the interleaved comb structures, and may accordingly act as barriers during subsequent depositions of materials.

Dense piers for three-dimensional memory arrays

A microelectronic device comprises a stack structure overlying a source tier. The stack structure comprising a vertically alternating sequence of conductive structures and insulative structures arranged in tiers. The microelectronic device comprises a staircase structure within the stack structure and having steps comprising lateral edges of the tiers, support structures vertically extending through the stack structure and within a horizontal area of the staircase structure, and conductive contacts vertically extending through the stack structure and horizontally neighboring the support structures within the horizontal area of the staircase structure. Each of the conductive contacts has a horizontally projecting portion in contact with one of the conductive structures of the stack structure at one of the steps of the staircase structure. Related memory devices, electronic systems, and methods of forming the microelectronic devices are also described.

Microelectronic devices including staircase structures, and related memory devices, electronic systems, and methods

Some embodiments include apparatuses and methods of forming the apparatuses. One of the apparatuses includes levels of conductive materials interleaved with levels of dielectric materials; memory cell strings including respective pillars extending through the levels of conductive materials and the levels of dielectric materials; a first dielectric structure formed in a first slit through the levels of conductive materials and the levels of dielectric materials; a second dielectric structure formed in a second slit through the levels of conductive materials and the levels of dielectric materials; the first dielectric structure and the second dielectric structure separating the levels of conductive materials, the levels of dielectric materials, and the pillars into separate portions, and the first and second dielectric structures including different widths.

Memory device including different dielectric structures between blocks

Integrated circuitry comprises two three-dimensional (3D) array regions individually comprising tiers of electronic components. A stair-step region is between the two 3D-array regions. First stair-step structures alternate with second stair-step structures along a first direction within the stair-step region. The first stair-step structures individually comprise two opposing first flights of stairs in a first vertical cross-section along the first direction. The stairs in the first flights each have multiple different-depth treads in a second vertical cross-section that is along a second direction that is orthogonal to the first direction. The second stair-step structures individually comprise two opposing second flights of stairs in the first vertical cross-section. The stairs in the second flights each have only a single one tread along the second direction. Other embodiments, including method, are disclosed.

Integrated circuitry, memory circuitry comprising strings of memory cells, and method of forming integrated circuitry

Some embodiments include methods of forming voids within semiconductor constructions. In some embodiments the voids may be utilized as microstructures for distributing coolant, for guiding electromagnetic radiation, or for separation and/or characterization of materials. Some embodiments include constructions having micro-structures therein which correspond to voids, conduits, insulative structures, semiconductor structures or conductive structures.

Methods of cooling semiconductor devices

Some embodiments include an integrated assembly having a first deck with first memory cells arranged in first tiers disposed one atop another, and having a second deck over the first deck and with second memory cells arranged in second tiers disposed one atop another. Cell-material-pillars pass through the first and second decks. The cell-material-pillars have first inter-deck inflections associated with a boundary between the first and second decks. The cell-material-pillars are arranged within a configuration which includes a first memory-block-region and a second memory-block-region. A panel is between the first and second memory-block-regions. The panel has a second inter-deck inflection associated with the boundary between the first and second decks. Some embodiments include methods of forming integrated assemblies.

Integrated assemblies and methods of forming integrated assemblies

Some embodiments include an integrated assembly having a pair of adjacent memory-block-regions, and having a separator structure between the adjacent memory-block-regions. The memory-block-regions include a first stack of alternating conductive levels and first insulative levels. The separator structure includes a second stack of alternating second and third insulative levels. The second insulative levels are substantially horizontally aligned with the conductive levels, and the third insulative levels are substantially horizontally aligned with the first insulative levels. Some embodiments include methods of forming integrated assemblies.

Integrated assemblies, and methods of forming integrated assemblies

A method of forming a semiconductor device comprises forming sacrificial structures and support pillars on a material. Tiers are formed over the sacrificial structures and support pillars and tier pillars and tier openings are formed to expose the sacrificial structures. One or more of the tier openings comprises a greater critical dimension than the other tier openings. The sacrificial structures are removed to form a cavity. A cell film is formed over sidewalls of the tier pillars, the cavity, and the one or more tier openings. A fill material is formed in the tier openings and adjacent to the cell film and a portion removed from the other tier openings to form recesses adjacent to an uppermost tier. Substantially all of the fill material is removed from the one or more tier openings. A doped polysilicon material is formed in the recesses and the one or more tier openings. A conductive material is formed in the recesses and in the one or more tier openings. An opening is formed in a slit region and a dielectric material is formed in the opening. Additional methods, semiconductor devices, and systems are disclosed.

Method of fabricating electronic devices comprising removing sacrificial structures to form a cavity

Integrated circuitry and methods

A transistor comprises channel material having first and second opposing sides. A gate is on the first side of the channel material and a gate insulator is between the gate and the channel material. A first insulating material has first and second opposing sides, with the first side being adjacent the second side of the channel material. A second insulating material of different composition from that of the first insulating material is adjacent the second side of the first insulating material. The second insulating material has at least one of (a), (b), and (c), where, (a): lower oxygen diffusivity than the first material, (b): net positive charge, and (c): at least two times greater shear strength than the first material. In some embodiments, an array of elevationally-extending strings of memory cells comprises such transistors. Other embodiments, including method, are disclosed.

Transistors and arrays of elevationally-extending strings of memory cells

Methods of forming electromagnetic radiation emitters and conduits

Methods of forming a memory device having an array portion including a plurality of array transistors and a periphery region including peripheral circuit transistor structures of the memory device, where an upper surface of the periphery region and an upper surface of the array portion are planar (or nearly planar) after formation of the peripheral circuit transistor structures and a plurality of memory cells (formed over the array transistors). The method includes forming the peripheral circuit transistor structures in the periphery region, forming the plurality of array transistors in the array portion and forming a plurality of memory cells over respective vertical transistors. Structures formed by the method have planar upper surfaces of the periphery and array regions.

Methods of forming vertical field-effect transistor with selfaligned contacts for memory devices with planar periphery/array and intermediate structures formed thereby

Growing community of inventors

Boise, ID, United States of America

David H Wells