Analog Devices,inc.

David H Robertson

Peter Real

David Byrd Ribner

Todd L Brooks

Christopher W Mangelsdorf

Paul F Ferguson, Jr

Douglas A Mercer

Apparajan Ganesan

Lawrence A Singer

David C Reynolds

Richard E Schreier

Carroll Clifton Speir

James C Camp

Iuri Mehr

Ernest T Stroud

Joseph Bradford Brannon

Theodore L Tewksbury

Sergei Nesterenko

Steve Harston

Anthony Del Muro

Embodiments of the present invention may provide a signal processing circuit that may comprises an analog-to-digital converter (ADC), and an output restriction circuit. The output restriction circuit may reduce the accuracy of the digital output of the ADC when signal content exceeds a pre-determined spectrum mask in an undesirable band. In one embodiment, the input signal spectrum may be actively monitored and when the input spectrum is inconsistent with an intended application, the output resolution may be restricted, for example, by truncating least significant bits (LSBs) of the digital output or adding digital noise.

Variable dynamic range receiver

Methods and apparatus for tuning are disclosed. One embodiment of the invention is directed to a tuner formed on a substrate. The tuner comprises a first die that receives an analog input signal and processes the analog input signal using analog processing circuitry to form analog output signals, and a second die that receives the analog output signals, converts the analog output signals to digital signals, and processes the digital signals to form output signals. Another embodiment of the invention is directed to a multi-chip module comprising a tuner adapted to process television signals of a plurality of types and of a plurality of standards to form output signals. A further embodiment of the invention is directed to a method that comprises receiving an analog signal from a signal source, filtering the analog signal to remove a portion of the analog signal, converting the analog signal to quadrature analog signals, converting the quadrature analog signals to digital signals, and filtering the digital signals to substantially isolate a channel of interest.

Methods and apparatus for tuning signals

Improved data scramblers and swapper cells and improved digital to analog converters are provided. The improved swapper cells permit data to be propagated through the cell immediately upon receipt. The determination of whether to swap data or pass it directly through is based on a history of data values propagated through the cell, but is independent of the values of the particular inputs being swapped. The data scrambler is structured to permit the possible data inputs on swapper cells in the scrambler to be restricted. A minimum delay data scrambler for use in a fast digital to analog converter is disclosed using these components.

Self-linearizing multi-bit DACs

An asymmetrical modem system wherein a modem at a first location transmits information to a modem at a second location on a downstream signal and the modem at the second location transmits information to the modem at the first location on an upstream signal. The system includes a first location transmitter section, having an N-point inverse frequency transform, for converting information into the downstream signal having up to (N/2)-1 carriers. A second location transmitter section having, an [(NL)/(2K)-point inverse frequency transform, converts information into the upstream analog signal having up to [(NL)/(2K)]-1 carriers, where K is the ratio of downstream signal bandwidth to upstream signal bandwidth and L is greater one. A receiver section at the first location, having an [NM/K]-point frequency transform, separates the upstream signal into up to [(NM)/(2K)]-1 upstream carriers, where M is greater than one. A receiver section at the second location, having an N-point frequency transform, separates the downstream analog signal into up to (N/2)-1 downstream carriers.

Asymmetric digital subscriber loop transceivers

A discrete multi-tone, asymmetrical transceiver and method wherein a modem at a central office transmits information to a modem at a remote terminal on a down-stream signal and the modem at the remote terminal transmits information to the modem at the central office on an up-stream signal. The up-stream signal comprising data carried by a lower portion of a predetermined band of frequencies and the down-stream signal comprising data carried by an upper portion of the predetermined band of frequencies. The system includes an interpolator, at the remote terminal, for adding interpolated data into a stream of data distributed by the remote terminal modem among the lower portion of the predetermined band of frequencies for transmission in the up-stream signal. An ADC is provided at the modem of the central office, for converting the down-stream signal into digital samples at a sampling rate greater than the frequency of the highest frequency in the down-stream signal. A decimator is fed samples from the ADC at the ADC sampling rate and produces output samples at a lower sampling rate. A demodulator is fed the samples produced by the decimator at the lower sampling rate and converts such samples into the lower portion of the predetermined band of frequencies. The interpolator increases the rate of samples produced on the up-stream signal and thereby increases the frequency of images in such up-stream signal for more effective removal by the band pass filter of the remote terminal. Images in the up-stream signal which may couple into the receiver at the central office are increased in frequency and then are effective filtering by the decimator.

Asymmetric digital subscriber loop transceiver and method

An ADC system includes a sigma-delta modulator that receives an analog input and provides a first digital output and an analog output. An ADC, coupled to the sigma-delta modulator, receives the analog output as an input and provides a second digital output. A digital processor, coupled to the sigma-delta modulator and the ADC, receives the first and second digital outputs and provides a digital representation of the analog input.

High speed sigma-delta analog-to-digital converter system

A circuit that produces a gate drive voltage for a MOS transistor switch includes an input that receives a supply voltage, a regulated voltage generating circuit that produces a regulated voltage, and a voltage storage element. A first switch connects the voltage storage element to sample one of the supply voltage and the regulated voltage during a first of first and second non-overlapping time intervals. The second switch connects the voltage storage element to increase the sampled voltage by another of the supply voltage and the regulated voltage to the gate drive voltage during the second non-overlapping time interval. A third switch connects the voltage storage element to provide the gate drive voltage to the MOS transistor switch during the second non-overlapping time interval. The regulated voltage generating circuit produces the regulated voltage such that a high level of the gate drive voltage exceeds the supply voltage yet is maintained less than a breakdown voltage of the MOS transistor switch.

Two-phase boosted CMOS switch drive technique and circuit

High-speed sigma-delta ADCs

A method and apparatus for operating an asymmetric digital subscriber loop modem system. A modem at a central office transmits information to a modem at a remote terminal on a down-stream signal having a predetermined bandwidth and the modem at the remote terminal transmits information to the modem at the central office on an up-stream signal having a bandwidth lower than the predetermined bandwidth of the down-stream signal. Digital samples of the up-stream signal in the central office modem are produced. Digital samples representative of an estimated echo signal in the central office modem are also produced. The digital samples of the up-stream signal and the digital samples representative of an estimated echo signal are both fed to a subtractor at the same rate. In a preferred embodiment, the up-stream signal is oversampled (i.e., is sampled at a rate greater than the Nyquist sampling rate) in producing the digital samples thereof. Samples of the down-stream signal are fed to an echo cancellation filter. The filter output is decimated to a predetermined rate. The samples of the oversampled up-stream signal are decimated producing samples at the predetermined rate. Both the decimated samples of the oversampled up-stream signal and the decimated samples of the filter are fed to the subtractor at the predetermined rate.

Asymmetric digital subscriber loop modem and method

A differential switch accepts a binary control signal and its complement (which may be skewed with respect to the control signal) and latches both signals simultaneously. The latched output signals drive the control terminals of a differential switch pair which connects one of two terminals to a third terminal, depending upon the state of the control terminals. The differential switch may optionally include an inverter which complements the binary control signal, thus eliminating the need for external inversion of the control signal. The switch is particularly applicable for use in a digital to analog converter.

Skewless differential switch and DAC employing the same

Gain linearity problems caused by impact ionization in a active MOS device are avoided by connecting an MOS shield device in series with the active MOS device so that the overall supply voltage is split across two devices, keeping both devices in a region of operation well below where impact ionization becomes a significant problem. The gate of the MOS shield device is maintained at a voltage proportional to its drain voltage, thereby keeping the device in the saturation mode and avoiding an abrupt mode change associated with prior art shield circuits.

Gain linearity correction circuit for MOS circuits

A sample-and-hold amplifier in which the held signal is represented as a voltage across a capacitor, but all other signals are represented as currents. At a summing node, the input current and a feedback current are summed to produce a difference current. In the tracking mode, this difference current flows through a closed hold switch onto the input of an integrator. The integrator accumulates the difference current onto the hold capacitor, where it becomes the hold voltage. This hold voltage is converted into a feedback current by a first transconductance amplifier, to provide the negative feedback to the summing node. The hold voltage, which need not equal the input signal, is also applied to the input of a second transconductance amplifier, which provides an output current. The ratio of the two transconductance gains determines the gain accuracy and linearity of the current output. When the hold switch is opened, there is no longer a current path into the hold capacitor, and the output current remains where it was at the moment the switch was opened.

Current mode sample-and-hold amplifier

Gain linearity correction for MOS circuits

A pipelined multi-stage ADC in which residue signals are passed between stages as currents. All sample-and-hold circuits are designed to be current-in/current-out structures; all but one also provide a voltage output. A voltage representation of the analog signal is provided as input to the flash converter within the quantization loop of each stage, allowing implementation of a conventional voltage comparator architecture in the flash converter. An extra comparator is added to the flash converter and an extra segment is included in the DAC of each stage. Inputs above full scale and below zero can be converted and generate output codes. Whenever the input goes above full scale or below zero, an out-of-range bit is set and the digital outputs are set to all ones or all zeroes, respectively. The combination of out-of-range bit and digital codes tell whether overranging or underranging occurred.

Analog-to-digital converter employing a pipeline multi-stage architecture

A reference voltage distribution system for use on an integrated circuit to distribute, from a reference voltage input, to remote locations on the chip, precise images of the reference voltage. The system comprises (1) a reference buffer located proximate a reference input connection and (2) a plurality of remote generator blocks, one located at each of the remotely-located sub-blocks or circuits requiring an image of the reference voltage. The reference buffer generates from the reference voltage a number of precision currents, each proportional to the reference voltage. These precision currents are routed to the remote generator blocks. Each remote generator block converts its precision current into a precision reference voltage for local use. These latter reference voltages may be the same as or different from the reference voltage supplied to chip itself.

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Somerville, MA, United States of America

David H Robertson