U.S. Philips Corporation

David H Paxman

Carole A Fisher

David J Coe

Philip H Bird

Franciscus A Schoofs

John A Slatter

Aart G Korteling

Michael J Moore

Reginald C Oldfield

Philip Walker

A semiconductor body (1) has a first region (2) of one conductivity type adjacent one major surface (3). Second and third regions (5 and 6) of the opposite conductivity type are provided within the first region (2) adjacent the one major surface (3) and an insulated gate structure (80) overlies a conduction channel region (9) between the second and third regions (5 and 6) for providing a gateable connection along the length (L) of the conduction channel region (9) between the second and third regions (5 and 6). The insulated gate structure (80) has a gate insulating region (81) and a gate conductive region (82) extending on the gate insulating region (81) and up onto a relatively thick insulating region (4) adjoining the gate insulating region (81). The gate insulating region (81) overlaps with the periphery (6a) of the portion (62) of the third region (6) adjacent the insulated gate structure (80) so that, in a direction (D) transverse to the length (L) of the conduction channel region (9), the gate conductive region (82) extends from the gate insulating region (81) up onto the relatively thick insulating region (4) over the first region (2). The corner (10b) at which the gate insulating region (81) adjoins the relatively thick insulating region (4) thus lies over the first region (2) and not over the third region (6), thereby reducing the electric field stress at the corner (10b).

Lateral insulated gate field effect semiconductor

A method of manufacturing a semiconductor device including both an enhancement (1) insulated gate field effect transistor (IGFET) and a depletion (2) mode IGFET is described. Impurities are introduced into a first region or epitaxial layer (4) of one conductivity type adjacent a given surface (3a) of a semiconductor body (3) to provide, for both the enhancement mode (1) and for the depletion mode (2) IGFET, a second region (5) of the opposite conductivity type adjacent the given surface, a source region (9) of a first conductivity type adjacent the given surface (3a) and surrounded by the second region (5) and a drain region (10) of the first conductivity type having a relatively lightly doped drain extension region (11) adjacent the given surface and extending toward the source region (9). First and second insulated gates (12) are provided on first and second areas (31a) and (31b), respectively, of the given surface to provide a respective gate connection between each source region and the associated drain region (10). The relative doses of impurities introduced to provide the second regions (5) and the relatively lightly doped drain extensions (11) received by the first area (31a) and the second area (31b) are independently controlled so as to provide adjacent the first area (31a) a channel area (13) of a second conductivity type and adjacent the second area (31b) a channel area (13') of the first conductivity type.

High voltage lateral enhancement IGFET

A method of manufacturing a semiconductor device including both an enhancement (1) insulated gate field effect transistor (IGFET) and a depletion (2) mode IGFET is described. Impurities are introduced into a first region or epitaxial layer (4) of one conductivity type adjacent a given surface (3a) of a semiconductor body (3) to provide, for both the enhancement mode (1) and for the depletion mode (2) IGFET, a second region (5) of the opposite conductivity type adjacent the given surface, a source region (9) of a first conductivity type adjacent the given surface (3a) and surrounded by the second region (5) and a drain region (10) of the first conductivity type having a relatively lightly doped drain extension region (11) adjacent the given surface and extending toward the source region (9). First and second insulated gates (12) are provided on first and second areas (31a) and (31b), respectively, of the given surface to provide a respective gate connection between each source region and the associated drain region (10). The relative doses of impurities introduced to provide the second regions (5) and the relatively lightly doped drain extensions (11) received by the first area (31a) and the second area (31b) are independently controlled so as to provide adjacent the first area (31a) a channel area (13) of a second conductivity type and adjacent the second area (31b) a channel area (13') of the first conductivity.

Method of manufacturing a semiconductor device

A semiconductor device and a circuit suitable for use in an intelligent power switch include an insulated gate field effect transistor (IGFET) (T2) and a power semiconductor switch (T1). The insulated gate field transistor IGFET (T2) is provided by a semiconductor body (6) which has a first region (7) of one conductivity type adjacent a given surface (6a) of the semiconductor body with the first region (7) forming at least part of a conductive path to a first main electrode of the power semiconductor switch. A second region (8) of the opposite conductivity type is provided within the first region adjacent the given surface (6a) and a third region (11) of the one conductivity type is provided adjacent the given surface (6a) within the second region (8), an area of the second region (8) underlying an insulated gate (14) provided on the given surface (6a) for defining a conduction channel (15) providing a gateable connection between the third region (11) and a fourth region (12) of the one conductivity type. The third and fourth regions (11 and 12) forming the source and drain regions of the IGFET and the second and third regions (8 and 11) together provide a zener diode, a conductive path being provided to the second region remote from the area underlying the insulated gate for reverse-biassing the zener diode. The IGFET may include a synchronous rectifier of a charge pump for providing a gate voltage signal to the power semiconductor switch which may be a power MOSFET (T2).

Semiconductor device and a circuit suitable for use in an intelligent

Low voltage semiconductor devices are integrated monolithically with a high voltage semiconductor device on an electrically conductive substrate. The substrate forms an electrode of the high voltage device and is connected in use to the high voltage terminal of a power supply. The low voltage devices operate from a regulated low voltage supply, which is regulated with reference to the high voltage supply voltage, and not with reference to ground. This reduces the need to isolate the low voltage devices from the conductive substrate. An intelligent power switch circuit constructed in accordance with the invention is suitable for use in automotive and lighting applications.

High voltage semiconductor with integrated low voltage circuitry

A method of manufacturing a semiconductor device such as a lateral insulated gate field effect transistor is described in which impurities for forming first and second relatively shallow RESURF regions (8 and 11) of the opposite and the one conductivity type, respectively, are then introduced into the first region (4) and the semiconductor body is then heated first in an oxidizing atmosphere to cause the impurities to diffuse to form the RESURF regions (8 and 11) and to grow a relatively thick layer of insulating material on the given surface (3) at the same time. The relatively thick layer of insulating material is then defined to provide field oxide (14a) and gate oxide (14) then grown onto which is deposited a conductive gate layer (15,16) to form an insulated gate structure. Impurities are then introduced into the semiconductor body (3) using the insulated gate structure as a mask so as to form a lateral insulated gate field effect transistor (1).

Method of manufacturing lateral IGFETS including reduced surface field

A method of manufacturing a semiconductor device in which a lateral insulated gate field effect transistor (IGFET) (1) is provided by defining an insulated gate structure (12) on a given surface (3a) of a semiconductor body (3) by providing an insulating layer on the given surface (3a) having a relatively thin region on a first area of the given surface adjoining a relatively thin region (14a) on a second area (31b) of the given surface and providing a conductive layer (15,16) on the insulating layer to define an insulated gate over the first area of the given surface with the conductive layer extending up onto the relatively thick region of the insulating layer. A window (26) is opened in the conductive layer on the relatively thick region of the insulating layer and the insulating layer is then etched isotropically through the window in the conductive layer to form a window (25) in the relatively thick region of the insulating layer thereby leaving part (29) of the conductive layer overhanging the edge of the window in the insulating layer. The conductive layer is then selectively etched with at least the area of the conductive layer spaced from the window masked so as to remove the part (29) overhanging the edge of the window (25) in the insulating layer. Impurities are then introduced using the insulated gate structure (12) as a part of a mask to form a source region (9) aligned with the insulated gate and a drain region (10) aligned with the window in the conductive layer (15, 16).

Method of manufacturing an insulated gate field effect transistor

A semiconductor device includes a bipolar transistor having an emitter region of one conductivity type formed in a base region of the opposite conductivity type, the base region being provided in a collector region of the one conductivity type. A first insulated gate field effect transistor provides a gateable connection to the emitter region of the bipolar transistor while a second insulated gate field effect transistor provides a charge extraction path from the base region when the bipolar transistor is turned off. The first insulated gate field effect transistor includes a further region of the other conductivity type provided in the emitter region, and a source region of the one conductivity type formed in the further region and an insulated gate overlying a channel area comprising at least part of the further region to provide a gateable connection between the emitter region and the source region of the first insulated gate field effect transistor. The second insulated gate field effect transistor having an insulated gate overlying a channel area comprising at least part of the emitter region adjacent the base region to provide a gateable connection between the base region and a source of the second insulated gate field effect transistor.

Semiconductor devices

A bipolar semiconductor device with interdigitated emitter and base regions has a sub-region of the base, which has a shorter carrier recombination time than the major part of the base region due to the presence of argon ion implantation induced carrier recombination centers. The sub-region of the base is located centrally with respect to the emitter region to intercept the transient current lines during device turn-off and so to promote collapse of the transient current and the avoidance of second breakdown of the device. The centrally located sub-region of the base is remote from the emitter region edges to collector region current flow when the device is on. The ions may be implanted at energies between 50 keV and 3 MeV and at doses between 10.sup.11 ions cm.sup.-2 and 10.sup.14 ions cm.sup.-2. The implanatation mask may be provided by photolithographically processed resist having a thickness between 0.5 .mu.m and 4 .mu.m dependant on the ion implantation energy. The depth of the sub region and the concentration of recombination centers within the sub-region may be varied by altering the implantation conditions to tailor the effect of the sub-region to the likelihood of the onset of second breakdown at any part of a device structure. The invention is particularly of use in transistors, and in thyristors.

Bipolar semiconductor devices with implanted recombination region

A semiconductor device, such as a gate turn-off thyristor, has, at a major surface of a semiconductor body a plurality of electrode fingers alternately contacting opposite conductivity type regions (e.g. the cathode and gate) of the semiconductor body. In order to save useful semiconductor area and to allow an improved electrode geometry bonding pads for the electrodes are formed at a level above the electrodes. An insulating layer separates the bonding pads and the electrodes. A first bonding pad contacts a first set of electrode fingers through a first set of windows in the insulating layer and a second bonding pad contacts a second set of electrode fingers through a second set of windows. In operation, the voltage drop along each electrode finger of a set is substantially equal. A third bonding pad may also contact the second electrode set through a third set of windows in the insulating layer.

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Redhill, United Kingdom

David H Paxman