Lsi Corporation

Lsi Logic Corporation

Veritas Technologies LLC

Opti, Inc.

David H Lin

Niranjan Sanjiv Pendharkar

Prasanna V Wakhare

Ben Sferrazza

The disclosed computer-implemented method for managing quality of service may include (i) providing, in a network storage environment, a quality of service engine to regulate network traffic by assigning three separate factors to applications that are consuming a network resource, (ii) adding, to a configuration of the quality of service engine, a fourth priority factor that establishes two tiers of priority among applications that generate traffic that is regulated by the quality of service engine, and (6) regulating, by the quality of service engine based on the fourth priority factor, network traffic in the network storage environment by providing access to the network resource to an application assigned a higher priority over another application assigned a lower priority such that the fourth priority factor enables the quality of service engine to adhere to a service level agreement. Various other methods, systems, and computer-readable media are also disclosed.

Systems and methods for managing quality of service

A method and system for prefetching sound data in a sound processor system. The method includes integrating a prefetching function into at least one voice engine by, providing a setup phase, a data processing phase, and a cleanup phase, and prefetching sound data from a memory during the cleanup phase. As a result, the prefetching of sound data is optimized.

Method and system for prefetching sound data in a sound processing system

The present invention provides a method and system for reducing power consumption of a sound processor. Aspects of the invention include providing a sound processor access to at least one register having a plurality of bits corresponding to sound operations capable of being performed by the sound processor; and allowing a host processor to write a value to at least a portion of the plurality of bits in the register during sound processing to selectively disable individual operations performed by the sound processor.

Method and system for reducing power consumption of a sound processor

A system and method for controlling access to parameter blocks of a sound processor. According to the method and system disclosed herein, the present invention includes a host, a sound processor coupled to the host, and at least two copies of a parameter block associated with the sound data. The sound processor can access a first copy of the at least two copies while the host is accessing a second copy of the at least two copies. As a result, parameter blocks are freely updated by the host processor and freely read by the sound processor without conflict and without performance loss.

System and method for controlling sound data

A dry/wet bit for controlling dry and wet components of an output sound during processing of an input sound is provided. The bit is configurable by a program to indicate when to reverse the dry and wet components of the output sound. When the bit has a first value, the dry component is calculated by modifying the input sound by an attenuation factor, and the wet component is calculated by providing to a reverberation filter as input the dry component modified by a reverberation factor. When the bit has a second value, the wet component is calculated by providing to the reverberation filter as input the input sound modified by the attenuation factor, and the dry component is calculated by modifying the input to the reverberation filter by the reverberation factor.

Single bit per-voice dry/wet reverb control

A system and method for implementing a sound processor. The sound processor includes a first voice engine, a second voice engine, and at least one single-port memory unit. An operation of the first voice engine and an operation of the second voice engine are time offset, wherein the time offset enables the first and second voice engines to share the at least one memory unit without contention. This results in cost savings and power consumption savings due to the smaller area needed for the memories.

Sound processor architecture using single port memory unit

An apparatus comprising a plurality of flip-flops and a compare circuit. The flip-flops may each be configured to (i) receive a clock signal and an input signal and (ii) generate an output signal. The flip-flops may be configured in series such that the output signal of a first of the flip-flops is presented as the input signal to a second of the flip-flops. The compare circuit may be configured to generate a reset signal in response to each of the output signals. The reset signal is generated until each of the output signals matches a set of predetermined values stored in the compare circuit.

Digital power-on reset

For use in a floating-point unit that supports floating-point formats having fractional parts of varying widths and employs a datapath wider than the fractional parts, a circuit and method for normalizing and rounding floating-point results and processor incorporating the circuit or the method. In one embodiment, the circuit includes: (1) left-shift circuitry for aligning a fractional part of the floating-point result with a most significant bit of the datapath and irrespective of a width of the fractional part to yield a shifted fractional part and (2) rounding circuitry, coupled to the shift circuitry, that rounds the shifted fractional part.

Circuit and method for normalizing and rounding floating-point results and processor incorporating the circuit or the method

A chipset is provided which permits reading and writing to cache tag memory for testing purposes and for writing non-cacheable tags into tag RAM entries to effectively invalidate the corresponding cache data entries.

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San Jose, CA, United States of America

David H Lin