Xerox Corporation

Teradata Corporation

David H Hartke

William D Turner

Philip M Neches

Jack E Shemer

David Cronshaw

Warren M Sterling

Robert Arthur Sprague

Wilbur E DuVall

James R Keddy

Richard J Baran

Darryl L Woodcock

Richard C Stockton

Alexandros C Papachristidis

Martin C Watson

A system for dynamically partitioning processors in a multiprocessor system intercoupled by a network utilizes, in association with each processor, a network accessible, locally changeable memory section. An available one of a number of common dynamic group addresses in each of the memories is reserved for a subgroup for the performance of subtasks within an overall task, and members of the group are designated as they receive messages to be processed. The members then locally update status words which establish membership, group validity and semaphore conditions, so that transactions may be initiated, coordinated and terminated with minimum involvement of processors that have no relevant subtasks. When the full task is completed the dynamic group is relinquished for use when a new task is to be undertaken. The system enables many tasks to be carried out concurrently with higher intercommunication efficiency.

Dynamically partitionable parallel processors

A system using a sorting network to intercouple multiple processors so as to distribute priority messages to all processors is characterized by semaphore means accessible to both the local processors and the global resource via the network. Transaction numbers identifying tasks are employed in the messages, and interfaces at each processor are locally controlled to establish transaction number related indications of the current status of each task being undertaken at the associated processor. A single query to all processors via the network elicits a prioritized response that denotes the global status as to that task. The transaction numbers also are used as global commands and local controls for the flow of messages. A destination selection system based on words in the messages is used as the basis for local acceptance or rejection of messages. This arrangement together with the transaction number system provides great flexibility as to intercommunication and control.

Multiprocessor intercommunication system and method

A proximity coupled electro-optic device in which the electro-optic element has a pattern of conductors applied to the surface thereof abutting the individually addressable electrodes applying encoded data samples. The conductors are aligned in the same, or substantially the same, direction as the electrodes, and the period of the conductor pattern is equal to or less than the maximum width of the electrodes. Directional alignment tolerances between the conductors and electrodes are increased as the period of the conductor pattern is decreased, and when the conductors are segmented.

Interface for proximity coupled electro-optic devices

The gap between the electrodes and the electro-optic element of a proximity coupled electro-optic device, such as a multi-gate light valve for an electro-optic line printer, is filled with a dielectric having a relative dielectric constant (i.e., the dielectric constant relative to that of air) which is substantially greater than 1, thereby reducing the effective electrical thickness of the gap which, in turn, enhances the proximity coupling.

Dielectric interface for proximity coupled electro-optic devices

Apparatus which reduces the cycle sequences of a buffer in order to meet high data merge rates by selective control of the chip enable inputs of a plurality of memory chips. During a write ones merge cycle, data patterns from a data-in register control the chip enable inputs of the memory chips and, simultaneously, a common data input line connected to the memory chips is held at logic one. After allowing sufficient time for address decoding of selected memory chips, a common memory write line of the memory chips is enabled to write ones into the selected words of the selected memory chips, while all the other memory chips are undisturbed since their chip enable inputs have not been activated.

Apparatus for overscribing binary data of a selected polarity into a

An autonomous processor for displaying on a video tube both text characters and facsimile data. To conserve memory space the facsimile data is stored in compressed form and is decompressed or unfolded in synchronism with the vertical and horizontal deflections in the video tube. Similarly the text characters are stored in coded form, together with interspaced commands, both inscribed in a list memory. Each character code in the list then selects an appropriate dot matrix from a font memory which also contains displacement data. Selected lines of the font dot matrices are then addressed by row coordinates to form a horizontal video signal, which is accumulated in a ping pong buffer concurrently unloading into a video register. This same video register merges the facsimile data which is concurrently unfolded.

Fax processor

Autonomous display processor

A distributed function processing system utilizing a conventional microprocessor operated as a text processor in combination with a plurality of other autonomous processing devices arranged to operate in a coherent processing system. One of the autonomous processors which is a memory control processor serves to periodically overlay a random access accelerator memory with the contents of a main memory system and concurrently resolves conflicts among various other autonomous memory service requests. This processor, therefore, accommodates the data rates of the main memory. The other processor is a display processor which generates signals to a video display system to provide a visual interface to the user and is therefore tied to the video rate. Accordingly, the processing burden is distributed within processors entailing differing rates operating autonomously. The memory control processor resolves and accommodates all of the memory service requests in the system and also performs control operations to support high speed I/O devices. Logic is provided to handle the other interrupts. Also, there is page mapping for context switching of a reference page and repeating logic for decoupling this processor from the other processors. This arrangement allows convenient expansion into plural work stations each sharing a common memory.

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David H Hartke