Harris Corporation

David H Damerow

William R Young

David Bruce Chester

Perry W Frogge

William F Johnstone

Richard A Yost

Denis W Faas

Cindy C Rauth

A system for communicating includes a transmitter that has an encoder and baseband modulator that encodes and modulates a sequence of data symbols as a payload data constellation to be communicated. A PN sequence generator and baseband modulator form a pilot signal as a training sequence with a periodically repeating spread spectrum sequence. A circuit superimposes the pilot signal over the sequence of data symbols to form a composite communication signal that is transmitted. A receiver receives the composite communication signal and extracts the pilot signal from the composite communication signal.

Spread baseband injected pilot carrier

A digital half-band filter with mutliplications using Wallace trees which have lower bits truncated for reduction in size and with a true/complementer providing saturation compensation together with accumulator overflow compensation by monitoring bits more significant than the output bits.

Half-band filter and method

A sequencer including input structure for receiving and retaining sequential data which includes the sequence starting address, the number of blocks in the sequence, the number of words in a block, increment between blocks and increment between words, includes an adder connected between the input structure and an output device and includes a controller for selectively providing to the adders inputs one or more of the sequence starting address, increment between words, increment between blocks and the output of the output device as a function of the number of blocks in the sequence and the number of words in a block.

Digital signal processing address sequencer

Decimation circuitry having a forward shifting data section receiving data samples in order including a plurality of forward decimation registers coupled in-line and providing a forward register output. Each forward decimation register operates as a first-in-first-out (FIFO) register having a decimation depth. A backward shifting data section includes a plurality of backward decimation registers having a decimation depth coupled in-line and providing a backward register output. One of the backward decimation registers which receives data samples in sequence from one of the forward decimation registers can function as both a last-in-first-out (LIFO) and a FIFO register, when a LIFO register, it operates to reverse blocks of data samples wherein the size of each block corresponds to the decimation rate. Each reversed block is then shifted through the backward shifting data section. Each of the other backward decimation registers operates as FIFO register. The decimation circuitry can be used to form a digital filter cascadable into various sizes.

Fold and decimate filter architecture

A sin/cos generator which stores values for sin X and cos X, multiplies the sin X and cos X by the value sin Y to produce partial products -sin Y sin X and sin Y cos X and adds the partial products sin Y cos X to sin X to produce sin (X+Y) and adds the partial products -sin Y sin X to cos X to produce cos (X+Y). The values of sin X and cos X are stored for a single quadrant without sign designation and quadrant control is provided to complement the appropriate values of sin X and cos X before adding and multiplying. The complementing forms the one's complement and adds a 1 in the least significant bit to form the two's complement.

Sin/cos generator implementation

A decoding signal processing mechanism preserves the use of a single high data rate encoder at a transmitter site, so that the input data may be continuously encoded and transmitted, while using multiple low data rate decoders at the receiver site in such a manner that 'end effects' are avoided and the performance of high data rate decoding is attained. At the transmitter site, digital information signals are encoded at a first encoding rate and then transmitted over a communication channel to a receiver site. At the receiver site signals to be decoded are coupled to a respective one of a plurality of decoders which decode, at a second rate less than said first, encoding rate, respective overlapping blocks of received encoded digital information signals and derive respective portions of the digital information signals. The decoded outputs of the decoders are combined to recover the digital information signals. To accommodate overlapping blocks of encoded information signals each decoder includes a buffer delay (memory) for storing a respective sequential overlapping portion of the received encoded information signal. By controlling the storage of a respective portion of the encoded signals through its buffer delay, each decoder can effectively operate on a portion of the encoded signals that permits downstream reassembly of the original information signals without anomolies at the signal interface of successive decoded segments of the information signals.

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Palm Bay, FL, United States of America

David H Damerow