Agilent Technologies, Inc.

Verigg Ipco

David H Armstrong

Ajay Khoche

Jochen Rivoir

William Richard Lawrence

An integrated circuit, including a configurable scan architecture used for an integrated circuit test procedure and quality control. The configurable scan chain architecture has the capability of being reconfigured to one of a variety scan chain architectures based on the constraints of the integrated circuit and the testing device. The present invention minimizes the integrated circuit test time by reconfiguring the scan architecture depending on certain constraints such as the latching frequency, the predetermined I/O frequency, the number of available integrated circuit I/O pins, the number of pins required for a proposed scan architecture, and the number of available pins on the testing device. The configurable scan architecture receives configuration signals which indicate which scan chain architecture should be configured on the integrated circuit that is being tested.

Bandwidth matching for scan architectures in an integrated circuit

An apparatus and method are provided for testing component tolerances of a device for testing integrated circuits. The testing device is generally characterized by a plurality of test connectors disposed at a test head, wherein each test connector carries electrical signals for a test channel. Further, each test channel generally corresponds to a circuit board that includes at least one driver and one receiver. In this general type of tester, a system is provided that includes a specialized DUT board that establishes a low impedance electrical connection (i.e., short) between electrical conductors of a first and second test connector. Through this low impedance path, a first driver from a first circuit board is directly connected (i.e., shorted) to a first receiver on a second circuit board. A controller is configured to control the first driver to output an electrical signal at a predetermined time. The preferred embodiment further includes evaluating mechanism designed to detect the signal received at the first receiver, and timing mechanism configured to time the signal delay. Specifically, the timing mechanism is configured to determine the length of time required to propagate the signal from the driver to the receiver. In accordance with the method aspect, the method includes the step of establishing an electrical connection between electrical conductors of a first and second test connector such that a first driver from a first circuit board is electrically connected across a low impedance path to a first receiver on a second circuit board. The method then controls the output of the first driver to drive an edge of an electrical signal at a predetermined time and detecting the signal received at the first receiver. Finally, the method determines whether the signal received at the first receiver is within a predetermined time period of the predetermined signal level output from the first driver.

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Boulder, CO, United States of America

David H Armstrong