Prime Computer Inc.

David H Albonesi

Brian K Langendorf

Michael J Homberg

John Chang

John G Faase

A method and apparatus for detecting an improper connection of one or more cables to signal a cable misconnection error. On a board at one end of the cable there is provided a transmit circuit unique to one of the pins or sockets of the connector and at the other end of the cable at an opposite board there is provided a receive circuit that, when the cable is properly connected, receives the signal from the transmit circuit. A misconnection of the cable eliminates the signal from the transmit circuit thus signaling an error at the receive circuit. In addition, semi-dedicated connector positions are also employed so as to assure a detection of a number of different misconnections of the cable, particularly in a multi-cable system.

Electric cable connection error-detect method and apparatus

The invention comprises a combined hardware and software method and apparatus for determining the size of memory located on a memory card inserted in the slot of a memory backplane of a computer system. The method and apparatus also provides a means for selecting the memory card which contains a requested memory location. Each memory slot has associated therewith a multibit code which indicates the size of the memory installed in the associated slot. The code from each slot is hardwired to the system memory controller which, given the codes can, as part of its memory initialization route, scan these bits and decode them in order to determine the amount of memory installed in each slot of the memory backplane. Each slot is further provided with an X-bit starting address which uniquely defines the lowest address available from the board inserted in the associated slot. The starting address from each slot is compared with the leftmost X-bits of the currently requested memory address. If the leftmost X-bits of the currently requested memory address are greater than the X-bit starting address of a given slot yet less than the X-bit starting address of the succeeding slot, then it is known that the given address must be contained on the given slot. The board containing the currently requested memory address can thereby be determined.

Memory board selection method and apparatus

The invention comprises a system bus apparatus and method for a multi-arm, multiprocessor computer system having a main memory and localized buffer cache memories at each processor. Each block of data in a cache includes tag bits which identifies the condition of the data block in relation to the corresponding data in main memory and other caches. The system bus (SYSBUS) comprises three subparts; 1) a MESSAGE/DATA bus, 2) a REQUEST/GRANT bus and 3) a BCU bus. The MESSAGE/DATA bus is coupled to every device on the system and is used for transferring messages, data and addresses. The REQUEST/GRANT bus couples between every device on an arm of the system and that arm's bus control unit (BCU). The BCU bus couples between the various BCUs. Both the MESSAGE/DATA bus and the BCU bus include ACK/NACK/HIT bits which are used when responding to messages received over the SYSBUS to inform the message-issuing device if the devices received the message and, if so, the condition of the data in relation to other caches and main memory. The protocol allows inconsistent copies of data to exist and prevents stale data from being used erroneously by monitoring the tag bits and the ACK/NACK/HIT bits. Further, under the appropriate conditions, a copy of the most recent data block may be transferred from one cache to another (with appropriate updating of tags) without updating the main memory. When a memory operation will bring about a situation where cache coherence can no longer be maintained, main memory is updated with the most recent copy of the data and the other caches are either updated or tagged as invalid.

System bus for multiprocessor computer system

A system for correcting soft memory failures such as alpha particle failures in a dynamic random access memory and in a computer system wherein writeback caches are employed in a system bus environment. The address field and source identification code associated with a detected data error are stored. A generic bus request signal is generated and upon a bus grant a read message is issued on the system bus having an address field and destination address code corresponding to the stored address field and source identification code. In response to the read message, the device indicated by the identification code writes back to memory the correct data corresponding to the address field.

Growing community of inventors

Hudson, MA, United States of America

David H Albonesi