University of Rochester

Other

Cornell University

International Business Machines Corporation

David H Albonesi

Rajeev Balasubramonian

Sandhya Dwarkadas

Alper Buyuktosunoglu

Grigorios Magklis

Greg P Semeraro

Michael L Scott

Christine A Shoemaker

Alper Buyuktosnoglu

Pradip Bose

Stanley Everett Schuster

Peter William Cook

Lei Chen

Paula Petrica

David M Brooks

Howard Chong

Adam M Izraelevitz

Brandon Hencey

Steve Dropsho

Methods, systems, and devices are disclosed for managing building power, in one aspect, a method for managing building power includes determining values for power usage of a heating, ventilation, or air conditioning (HVAC) system in one or more zones of a building, the values including a cost of power value, a comfort value, a weighting function between the cost of power value and the comfort value, or a thermal storage value, in which the determining the values is based on a plurality of parameters including a price of power, a time of use, a total power allocation, or random variables including weather and building occupancy factors, and determining a power level for a plurality of states based on the determined values, the plurality of states corresponding to different levels of power to operate the HVAC system in the one or more zones.

Building power management systems

The present disclosure provides methods and systems for managing power in a processor having multiple cores. In one implementation, a microarchitecture of a core within a general-purpose processor may include configurable lanes (horizontal slices through the pipeline) which can be powered on and off independently from each other within the core. An online optimization algorithm may determine within a reasonably small fraction of a time slice a combination of lanes within different cores of the processor to be powered on that optimizes performance under a power constraint budget for the workload running on the general-purpose processor. The online optimization algorithm may use an objective function based on response surface models constructed to fit to a set of sampled data obtained by running the workload on the general-purpose processor with multiple cores, without running the full workload. In other implementations, the power supply to lanes can be gated.

Multi-core computer processor based on a dynamic core-level power management for enhanced overall power efficiency

In a processor having multiple clusters which operate in parallel, the number of clusters in use can be varied dynamically. At the start of each program phase, the configuration option for an interval is run to determine the optimal configuration, which is used until the next phase change is detected. The optimum instruction interval is determined by starting with a minimum interval and doubling it until a low stability factor is reached.

Performance monitoring for new phase dynamic optimization of instruction dispatch cluster configuration

A cache and TLB layout and design leverage repeater insertion to provide dynamic low-cost configurability trading off size and speed on a per application phase basis. A configuration management algorithm dynamically detects phase changes and reacts to an application's hit and miss intolerance in order to improve memory hierarchy performance while taking energy consumption into consideration.

Dynamic reconfigurable memory hierarchy

A method and structure of reducing power consumption in a microprocessor includes at least one storage structure in which the activity of the storage structure is dynamically measured and the size of the structure is controlled based on the activity. The storage structure includes a plurality of blocks, and the size of the structure is controlled in units of block size, based on activity measured in the blocks. An exemplary embodiment is an adaptive out-of-order queue.

Adaptive issue queue for reduced power at high performance

Memory hierarchy reconfiguration for energy and performance in general-purpose processor architectures

A multiple clock domain (MCD) microarchitecture uses a globally-asynchronous, locally-synchronous (GALS) clocking style. In an MCD microprocessor each functional block operates with a separately generated clock, and synchronizing circuits ensure reliable inter-domain communication. Thus, fully synchronous design practices are used in the design of each domain.

Multiple clock domain microprocessor

A data dependence table in RAM relates physical register addresses to instructions such that for each instruction, the registers on whose data the instruction depends are identified. The table is updated for each instruction added to the pipeline. For a branch instruction, the table identifies the registers relevant to the branch instruction for branch prediction.

Dynamic data dependence tracking and its application to branch prediction

Multi-cluster processor operating only select number of clusters during each phase based on program statistic monitored at predetermined intervals

A complexity-adaptive hardware/software system and method for a microprocessor to execute any of a plurality of diverse applications according to a predetermined instruction set architecture. The system includes dynamic hardware structures and configurable clocking system of the microprocessor for executing any particular application among the plurality of diverse applications, the dynamic hardware structures and configurable clocking system being adaptable to be organized in any of a plurality of potential configurations which are selectable according to the particular application to be executed. Configuration control is performed in response to the particular application to be executed, the instruction set architecture, and the potential configurations in which the dynamic hardware structures and configurable clocking system may be organized. The control is exercised by configuring an organization of the dynamic hardware structures and configurable clocking system to match the particular application to be executed during execution thereof. The dynamic hardware structures and configurable clocking system are reconfigured to a different organization for a match when another application is being executed, or even in the course of execution of the same application. In this way, the hardware implementation is adaptive to optimize performance of the microprocessor according to each particular application being executed among the plurality of diverse applications that may be executed.

Mechanism for dynamically adapting the complexity of a microprocessor

Growing community of inventors

Ithaca, NY, United States of America

David H Albonesi