Analog Devices,inc.

David Graham Nairn

Colin Gerard Lyden

John Jude O'Donnell

Christopher Michalski

Converter systems are provided that use particular combinations of fixed and variable clock skewers to generate interleaved clock signals for the systems. These combinations have been found effective in accurately generating selectively-skewed clocks while simultaneously restricting the jitter that generally accompanies the skewing process.

Converter systems having reduced-jitter, selectively-skewed interleaved clocks

The present invention relates to a method and system for reducing integral non linearity errors in a pipeline Analog to Digital Converter (ADC). The invention provides in a first embodiment a method comprising the steps of: adding an analog dither signal to the analog input signal of a pipeline Analog to Digital Converter, and converting the analog input signal to a digital output signal by means of the pipeline Analog to Digital Converter. The amplitude of the analog dither signal is determined by the architecture of the Analog to Digital Converter. The invention also provides in a second embodiment a circuit comprising a pipeline analog to digital converter for converting an analog input signal to a digital output signal and a feedback circuit coupled to the converter such that the digital output signal is adapted to have an average non linearity error value of about zero LSBs.

INL curve correction in a pipeline ADC

A multi-channel analog-to-digital converter system includes an array of sub-analog-to-digital converters wherein within the array of sub-analog-to-digital converters, there is at least one designated reference analog-to-digital converter. The analog-to-digital converter system also includes a non-sequential channel select circuit to control a selection of the analog-to-digital converters and the reference analog-to-digital converter to non-sequentially interleave the outputs of said analog-to-digital converters and said reference analog-to-digital converter. Each channel of the plurality of sub-analog-to-digital converters includes a timing skew estimation circuit. Each timing skew estimation circuit receives an output signal from the reference analog-to-digital converter and receives the output signal from the associated analog-to-digital converter. Each timing skew estimation circuit generates a timing signal to be used in shifting or adjusting the actual or apparent sample times for the appropriate analog-to-digital converter.

System and method for using timing skew estimation with a non-sequential time-interleaved analog-to-digital converter

Comparator systems are provided that include cross-coupled transistors which respond to a differential network that receives an input signal. The systems further include a control transistor connected across the cross-coupled transistors and a bias network configured to apply a bias voltage to the control transistor that is substantially the voltage across two transistors which are each biased into saturation. It has been found that this bias during the systems' acquire phase substantially stabilizes the systems' gain over variations in their total environment and that this stabilization enhances the systems' performance.

Stable systems for comparing and converting signals

Time-interleaved signal converter systems are provided that multiplex respective digital sequences of system converters into an interleaved digital sequence before filtering each respective digital sequence with digital filters that apply respective filter coefficients to thereby reduce system degradation caused by converter timing skews. Use of the interleaved digital sequence in the filtering process substantially increases the system bandwidth from approximately one half of the converter sample rate Rto approximately one half of a greater system sample rate R. Converter system embodiments are preferably configured to reduce large timing skews prior to filtering the interleaved digital sequence to obtain further reduction. This combined approach has been found to enhance interleaved system performance.

Time-interleaved signal converter systems with reduced timing skews

A comparator includes a circuit which provides a plurality of common-mode difference signals in response to differential input signals. The circuit provides a common-mode feedback signal in response to the plurality of common-mode difference signals. The common-mode feedback signal is used to drive the common-mode level of an amplifier to a desired value.

Differential amplifier with reduced common-mode and method

Methods and controllers are provided to estimate and reduce phase errors between converters of time-interleaved analog-to-digital systems by generating corresponding error signals in the form of difference signals. The difference signals concern differences between magnitudes of first adjacent samples and interleaved second adjacent samples of the converters. The difference signals can be applied (e.g., to a converter's input sampler or to a variable delay element inserted after the converter) to substantially reduce the phase errors. The methods and controllers may be economically implemented because they can be realized with simple operations (e.g., addition and subtraction). Although some embodiments are facilitated with knowledge of parameters of the analog input signal, others do not require this knowledge so long as the signal is restricted to lie within a single Nyquist zone.

Phase-error reduction methods and controllers for time-interleaved analog-to-digital systems

A circuit with a common-mode dual output includes a feedback circuit connected to alternate the states of the dual output between an average output level and a desired common-mode level. The difference between the average and desired levels is proportional to a signal offset level. An impedance matching circuit is connected to the feedback circuit to adjust the signal offset level.

Switched capacitor circuit with reduced common-mode variations

Timing enhancements of embodiments of the invention are realized in time-interleaved converter systems with minimal network additions that facilitate the insertion of a timing signal into the system's input analog signal. The timing signal travels with the input analog signal so that it continues to accurately define predetermined sample times in the analog signal even as they travel over different path lengths to individual converters. Each converter has a feedback path which adjusts the timing of that converter's samples with a correction signal whose value is determined by contributions of first and second different amplitudes of the timing signal to that converter's output signals.

Timing enhancement methods and networks for time-interleaved analog-to-digital systems

A signal conditioning system includes first and second converters coupled to a random clock which provides a random sampling rate. Corresponding offset sensor coupled with the first and second converters sense and adjust an offset signal difference. A gain sensor is coupled with the first and second converters to sense a gain difference between the first and second converters and a gain corrector is coupled with the gain sensor to adjust the gain difference.

Signal conditioning system with adjustable gain and offset mismatches

Parallel analog-to-digital converter systems are provided in which converters are temporally interleaved. In particular, converters are partitioned into at least two converter groups which are assigned different respective group converter periods that are multiples of the system periods. With converters in each of the converter groups, respective samples are processed over that group's respective group converter period and the group converter periods of all converters are temporally shifted to process each of the samples with at least one of the converters. System spurious signals are thus reduced and, in another system embodiment, the reduced spurious lines are converted into the system's noise level by detecting instances when available converters that belong to different converter groups are available to process an upcoming one of the samples and, in at least a chosen one of the instances, exchanging the available converters between their different converter groups to thereby alter which processes the upcoming sample and which processes a subsequent sample. All converters continue to process respective samples.

Temporally-interleaved parallel analog-to-digital converters and methods

High-speed sampler methods and structures are provided to enhance the correlation between an input signal S and a corresponding sampler output voltage V . An input buffer is enabled during sampling time periods and disabled during holding time periods. In the sampling time periods, a sampling capacitor C is directly charged through the input buffer and the capacitor's bottom plate to a charge that corresponds to the input signal S . In the holding time periods, the disabled input buffer is isolated from the sampling capacitor C and a common-mode signal S is directly coupled to the capacitor's bottom plate to provide the output voltage V at the capacitor's top plate. Preferably, an output capacitor C is coupled to the sampling capacitor C and charge from the sampling capacitor C is transferred to the output capacitor C .

High-speed sampler structures and methods

A sample and hold circuit having a semiconductor with a field effect transistor therein. The field effect transistor has a channel in the semiconductor, a source region in the semiconductor, a drain region in the semiconductor a front-gate disposed over the channel, and a back-gate in the semiconductor under the channel. The front-gate and back-gate are configured to control a flow of carriers in the semiconductor through a length of the channel between the source region and the drain region. A capacitor is connected to one of the drain and source regions. The other one of the source and drain region is configured for coupling to an input signal. A switch is responsive to a sampling signal to electrically connect a constant electrical potential between one of the source and drain regions and back-gate during a tracking phase. In one embodiment, the sample and hold circuit includes a second switch to electrically a second constant potential between the front-gate and one of the source and drain. With such an arrangement, non-linearities arising from variations in both the voltage between the source/drain and back-gate (V,) and between the source/drain and front-gate (V,) are compensated leading to a more linear sample and hold circuit. In a second embodiment, the second switch electrically connects a fixed potential to the front-gate during the tracking phase. With such an arrangement, non-linearities arising from variations in the voltage between the source/drain and back-gate (V,) are compensated leading to a more linear sample and hold circuit. Further, because the non-linearities due to V,are dealt with, the need for a large (V,) (with the potential for voltages exceeding the supply voltage) is reduced. Hence circuit according to the invention yields reduced harmonic distortion without the need for large on-chip voltages.

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Greensboro, NC, United States of America

David Graham Nairn